| 8782287 |
Methods and apparatus for using multiple reassembly memories for performing multiple functions |
Gregg A. Bouchard, Joel Roger Davidson, Michael Hathaway, James T. Kirk, Christopher Brian Walton |
2014-07-15 |
| 8497694 |
On-chip sensor for measuring dynamic power supply noise of the semiconductor chip |
Lew G. Chua-Eoan, Boris Andreev, Christopher T. Phan, Amirali Shayan, Xiaohua Kong +2 more |
2013-07-30 |
| 7246102 |
Method of improving the lookup performance of three-type knowledge base searches |
Betty A. McDaniel, William E. Baker, Narender Vangati, James T. Kirk |
2007-07-17 |
| 7113518 |
Processor with reduced memory requirements for high-speed routing and switching of packets |
Joel Roger Davidson, Michael Hathaway, James T. Kirk |
2006-09-26 |
| 7088719 |
Processor with packet processing order maintenance based on packet flow identifiers |
David Allen Brown, Abraham Prasad |
2006-08-08 |
| 7079539 |
Method and apparatus for classification of packet data prior to storage in processor buffer memory |
Joel Roger Davidson, Betty A. McDaniel |
2006-07-18 |
| 7043544 |
Processor with multiple-pass non-sequential packet classification feature |
William E. Baker, James T. Kirk, Betty A. McDaniel |
2006-05-09 |
| 6944731 |
Dynamic random access memory system with bank conflict avoidance feature |
Gregg A. Bouchard, Ravi Ramaswami |
2005-09-13 |
| 6915480 |
Processor with packet data flushing feature |
Joel Roger Davidson, James T. Kirk, Betty A. McDaniel, Maurice A. Uebelhor |
2005-07-05 |
| 6839797 |
Multi-bank scheduling to improve performance on tree accesses in a DRAM based random access memory subsystem |
Ravi Ramaswami |
2005-01-04 |
| 6804692 |
Method and apparatus for reassembly of data blocks within a network processor |
Joel Roger Davidson, James T. Kirk |
2004-10-12 |
| 6134650 |
Apparatus and method for predicting a first scanned instruction as microcode instruction prior to scanning predecode data |
Gerald D. Zuraski, Jr., Shane Southard |
2000-10-17 |
| 6061775 |
Apparatus and method for predicting a first microcode instruction of a cache line and using predecode instruction data to identify instruction boundaries and types |
Thang M. Tran, Shane Southard |
2000-05-09 |
| 5890006 |
Apparatus for extracting instruction specific bytes from an instruction |
Thang M. Tran, Shane Southard |
1999-03-30 |