Issued Patents All Time
Showing 25 most recent of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12256547 | Silicon oxide nitride tunnel dielectric for a storage transistor in a 3-dimensional NOR memory string array | Scott Brad Herner, Christopher J. Petti, Wu-Yi Henry Chien | 2025-03-18 |
| 12183834 | Cool electron erasing in thin-film storage transistors | Sayeef Salahuddin, Wu-Yi Henry Chien, Eli Harari | 2024-12-31 |
| 12160996 | Three-dimensional memory string array of thin-film ferroelectric transistors | Christopher J. Petti, Vinod R. Purayath, Wu-Yi Henry Chien, Eli Harari | 2024-12-03 |
| 11839086 | 3-dimensional memory string array of thin-film ferroelectric transistors | Christopher J. Petti, Vinod R. Purayath, Wu-Yi Henry Chien, Eli Harari | 2023-12-05 |
| 11515432 | Cool electron erasing in thin-film storage transistors | Sayeef Salahuddin, Wu-Yi Henry Chien, Eli Harari | 2022-11-29 |
| 11069696 | Device structure for a 3-dimensional NOR memory array and methods for improved erase operations applied thereto | Eli Harari, Raul-Adrian Cernea, Wu-Yi Henry Chien | 2021-07-20 |
| 10896916 | Reverse memory cell | Eli Harari, Yupin Fong | 2021-01-19 |
| 9721653 | Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture | Tianhong Yan | 2017-08-01 |
| 9672916 | Operation modes for an inverted NAND architecture | Yanli Zhang, Johann Alsmeier, Jian Chen | 2017-06-06 |
| 9466790 | Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines | — | 2016-10-11 |
| 9330763 | Operation modes for an inverted NAND architecture | Yanli Zhang, Johann Alsmeier, Jian Chen | 2016-05-03 |
| 9331181 | Nanodot enhanced hybrid floating gate for non-volatile memory devices | Donovan Lee, James Kai, Henry Chien, George Matamis, Vinod R. Purayath | 2016-05-03 |
| 9245629 | Method for non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines | Luca Fasoli, Masaaki Higashitani, Roy E. Scheuerlein | 2016-01-26 |
| 9236122 | Shared-gate vertical-TFT for vertical bit line array | Tianhong Yan, Tz-Yi Liu, Tim Chen, Perumal Ratnam | 2016-01-12 |
| 9227456 | Memories with cylindrical read/write stacks | Henry Chien, Yao-Sheng Lee, Johann Alsmeier | 2016-01-05 |
| 9190134 | Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture | — | 2015-11-17 |
| 9165940 | Three dimensional NAND device with silicide containing floating gates and method of making thereof | Henry Chien, Johann Alsmeier, Henry Chin, George Matamis, Yuan Zhang +3 more | 2015-10-20 |
| 9147439 | Non-volatile memory having 3D array architecture with staircase word lines and vertical bit lines and methods thereof | Raul-Adrian Cernea | 2015-09-29 |
| 9064547 | 3D non-volatile memory having low-current cells and methods | Raul-Adrian Cernea, Yung-Tin Chen | 2015-06-23 |
| 9047983 | Temperature compensation of conductive bridge memory arrays | Roy E. Scheuerlein | 2015-06-02 |
| 9029936 | Non-volatile memory structure containing nanodots and continuous metal layer charge traps and method of making thereof | Vinod R. Purayath, George Matamis, James Kai, Yuan Zhang | 2015-05-12 |
| 8958228 | Non-volatile memory having 3D array of read/write elements with vertical bit lines and select devices and methods thereof | Johann Alsmeier | 2015-02-17 |
| 8928061 | Three dimensional NAND device with silicide containing floating gates | Henry Chien, Johann Alsmeier, Henry Chin, George Matamis, Yuan Zhang +3 more | 2015-01-06 |
| 8822288 | NAND memory device containing nanodots and method of making thereof | Vinod R. Purayath, George Matamis, James Kai, Yuan Zhang | 2014-09-02 |
| 8824183 | Non-volatile memory having 3D array of read/write elements with vertical bit lines and select devices and methods thereof | Johann Alsmeier | 2014-09-02 |