DH

David S. Hutton

IBM: 35 patents #2,774 of 70,183Top 4%
Overall (All Time): #93,910 of 4,157,543Top 3%
36
Patents All Time

Issued Patents All Time

Showing 25 most recent of 36 patents

Patent #TitleCo-InventorsDate
10884754 Infinite processor thread balancing Gregory W. Alexander, Stephen Duffy, Christian Jacobi, Anthony Saporito, Somin Song 2021-01-05
10599431 Managing backend resources via frontend steering or stalls Gregory W. Alexander, Christian Jacobi, Edward T. Malley, Anthony Saporito 2020-03-24
10558464 Infinite processor thread balancing Gregory W. Alexander, Stephen Duffy, Christian Jacobi, Anthony Saporito, Somin Song 2020-02-11
10540183 Accelerated execution of execute instruction target Khary J. Alexander, Fadi Y. Busaba, Brian W. Curran, Edward T. Malley, Brian R. Prasky +1 more 2020-01-21
10365928 Suppress unnecessary mapping for scratch register Gregory W. Alexander, Christian Jacobi, Edward T. Malley, Anthony Saporito 2019-07-30
10013257 Register comparison for operand store compare (OSC) prediction Wen H. Li, Eric M. Schwarz 2018-07-03
9875107 Accelerated execution of execute instruction target Khary J. Alexander, Fadi Y. Busaba, Brian W. Curran, Edward T. Malley, Brian R. Prasky +1 more 2018-01-23
9766896 Optimizing grouping of instructions Fadi Y. Busaba, Michael T. Huffer, Edward T. Malley, John G. Rell, Jr., Eric M. Schwarz +1 more 2017-09-19
9760379 Register comparison for operand store compare (OSC) prediction Wen H. Li, Eric M. Schwarz 2017-09-12
9710278 Optimizing grouping of instructions Fadi Y. Busaba, Michael T. Huffer, Edward T. Malley, John G. Rell, Jr., Eric M. Schwarz +1 more 2017-07-18
9710281 Register comparison for operand store compare (OSC) prediction Wen H. Li, Eric M. Schwarz 2017-07-18
9626189 Reducing operand store compare penalties Fadi Y. Busaba, John G. Rell, Jr., Chung-Lung K. Shum 2017-04-18
9524165 Register comparison for operand store compare (OSC) prediction Wen H. Li, Eric M. Schwarz 2016-12-20
9389865 Accelerated execution of target of execute instruction Khary J. Alexander, Fadi Y. Busaba, Brian W. Curran, Edward T. Malley, Brian R. Prasky +1 more 2016-07-12
8938605 Instruction cracking based on machine state Fadi Y. Busaba, Bruce C. Giamei, Eric M. Schwarz 2015-01-20
8874885 Mitigating lookahead branch prediction latency by purposely stalling a branch instruction until a delayed branch prediction is received or a timeout occurs James J. Bonanno, Brian R. Prasky, Anthony Saporito 2014-10-28
8566529 Method, system and computer program product for generalized LRU in cache and memory performance analysis and modeling Keith N. Langston, Kathryn Marie Jackson, Hanno Ulrich, Craig R. Walters 2013-10-22
8464030 Instruction cracking and issue shortening based on instruction base fields, index fields, operand fields, and various other instruction text bits Fadi Y. Busaba, Brian W. Curran, Lee Evan Eisen, Bruce C. Giamei 2013-06-11
8453124 Collecting computer processor instrumentation data Gregory W. Alexander, Jane H. Bartik, Michael Billeci, Christian Jacobi, Jang-Soo Lee +3 more 2013-05-28
8443176 Method, system, and computer program product for reducing cache memory pollution Robert J. Sonnelitter, III, James J. Bonanno, Brian R. Prasky, Anthony Saporito 2013-05-14
8423968 Template-based vertical microcode instruction trace generation Jane H. Bartik 2013-04-16
8195924 Early instruction text based operand store compare reject avoidance Khary J. Alexander, Fadi Y. Basuba, Bruce C. Giamei, Chung-Lung K. Shum 2012-06-05
8131945 Disowning cache entries on aging out of the entry Kathryn Marie Jackson, Keith N. Langston, Pak-kin Mak, Chung-Lung K. Shum 2012-03-06
7975130 Method and system for early instruction text based operand store compare reject avoidance Khary J. Alexander, Fadi Y. Busada, Bruce C. Giamei, Chung-Lung K. Shum 2011-07-05
7971034 Reduced overhead address mode change management in a pipelined, recycling microprocessor Michael Billeci, Fadi Y. Busaba, Brian R. Prasky, John G. Rell, Jr., Chung-Lung K. Shum +1 more 2011-06-28