Issued Patents All Time
Showing 25 most recent of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12400144 | Machine learning for computational patterning | Julian Timothy Dolby | 2025-08-26 |
| 12135497 | Random weight initialization of non-volatile memory array | Takashi Ando, Reinaldo Vega, Praneet Adusumilli | 2024-11-05 |
| 11916014 | Gate contact inside gate cut trench | Reinaldo Vega, Takashi Ando, Praneet Adusumilli | 2024-02-27 |
| 11621333 | Gate contact structure for a transistor device | Ruilong Xie, Hao Tang, Daniel Chanemougame, Lars Liebmann, Mark V. Raymond | 2023-04-04 |
| 11527647 | Field effect transistor (FET) devices | Reinaldo Vega, Takashi Ando, Praneet Adusumilli | 2022-12-13 |
| 11508823 | Low capacitance low RC wrap-around-contact | Ruilong Xie, Ekmini Anuja De Silva, Jing Guo, Hao Tang | 2022-11-22 |
| 11205592 | Self-aligned top via structure | Ruilong Xie, Chih-Chao Yang, Kangguo Cheng | 2021-12-21 |
| 10916650 | Uniform bottom spacer for VFET devices | Steven R. Bentley, Chanro Park, Ruilong Xie, Tenko Yamashita | 2021-02-09 |
| 10832943 | Gate contact over active region with self-aligned source/drain contact | Su Chen Fan, Kangguo Cheng, Ruilong Xie | 2020-11-10 |
| 10763342 | Semiconductor devices having equal thickness gate spacers | Ruilong Xie | 2020-09-01 |
| 10727308 | Gate contact structure for a transistor | Ruilong Xie, Hao Tang, Daniel Chanemougame, Lars Liebmann, Mark V. Raymond | 2020-07-28 |
| 10665586 | Method of concurrently forming source/drain and gate contacts and related device | Ruilong Xie | 2020-05-26 |
| 10658459 | Nanosheet transistor with robust source/drain isolation from substrate | Robin Hsin Kuo Chao, Kangguo Cheng, Ruilong Xie, John H. Zhang | 2020-05-19 |
| 10622475 | Uniform bottom spacer for VFET devices | Steven R. Bentley, Chanro Park, Ruilong Xie, Tenko Yamashita | 2020-04-14 |
| 10593782 | Self-aligned finFET formation | Fee Li Lie, Chi-Chun Liu, Ruilong Xie | 2020-03-17 |
| 10490641 | Methods of forming a gate contact structure for a transistor | Ruilong Xie, Hao Tang, Daniel Chanemougame, Lars Liebmann, Mark V. Raymond | 2019-11-26 |
| 10483363 | Methods of forming a gate contact structure above an active region of a transistor | Ruilong Xie, Hao Tang, Daniel Chanemougame, Lars Liebmann, Mark V. Raymond | 2019-11-19 |
| 10475660 | Method for fin formation with a self-aligned directed self-assembly process and cut-last scheme | Fee Li Lie, Chi-Chun Liu, Ruilong Xie | 2019-11-12 |
| 10461174 | Vertical field effect transistors with self aligned gate and source/drain contacts | Hao Tang, Ruilong Xie | 2019-10-29 |
| 10431651 | Nanosheet transistor with robust source/drain isolation from substrate | Robin Hsin Kuo Chao, Kangguo Cheng, Ruilong Xie, John H. Zhang | 2019-10-01 |
| 10418485 | Forming a combination of long channel devices and vertical transport Fin field effect transistors on the same substrate | Tenko Yamashita, Chen Zhang | 2019-09-17 |
| 10411127 | Forming a combination of long channel devices and vertical transport fin field effect transistors on the same substrate | Tenko Yamashita, Chen Zhang | 2019-09-10 |
| 10395939 | Method for fin formation with a self-aligned directed self-assembly process and cut-last scheme | Fee Li Lie, Chi-Chun Liu, Ruilong Xie | 2019-08-27 |
| 10366931 | Nanosheet devices with CMOS epitaxy and method of forming | Ruilong Xie, Pietro Montanini, Tenko Yamashita, Nicolas Loubet | 2019-07-30 |
| 10361315 | Method and apparatus of fabricating source and drain epitaxy for vertical field effect transistor | Chun-Chen Yeh, Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chen Zhang | 2019-07-23 |