Issued Patents All Time
Showing 76–100 of 211 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11093247 | Systems and methods to load a tile register pair | Raanan Sade, Simon Rubanovich, Amit Gradstein, Alexander Heinecke, Robert Valentine +5 more | 2021-08-17 |
| 11086623 | Systems, methods, and apparatuses for tile matrix multiplication and accumulation | Robert Valentine, Mark J. Charney, Bret L. Toll, Rinat Rappoport, Stanislav Shwartsman +7 more | 2021-08-10 |
| 11080048 | Systems, methods, and apparatus for tile configuration | Menachem Adelman, Robert Valentine, Mark J. Charney, Bret L. Toll, Rinat Rappoport +6 more | 2021-08-03 |
| 11068263 | Systems and methods for performing instructions to convert to 16-bit floating-point format | Alexander Heinecke, Robert Valentine, Mark J. Charney, Raanan Sade, Menachem Adelman +2 more | 2021-07-20 |
| 11068262 | Systems and methods for performing instructions to convert to 16-bit floating-point format | Alexander Heinecke, Robert Valentine, Mark J. Charney, Raanan Sade, Menachem Adelman +2 more | 2021-07-20 |
| 11048587 | Apparatus and method for detecting and recovering from data fetch errors | Theodros Yigzaw, Geeyarpuram N. Santhanakrishnan, Ganapati Srinivasa, Jose A. Vargas, Hisham Shafi +5 more | 2021-06-29 |
| 11036509 | Enabling removal and reconstruction of flag operations in a processor | Tomer Weiner, Amit Gradstein, Simon Rubanovich, Alex Gerber, Itai Ravid | 2021-06-15 |
| 11036504 | Systems and methods for performing 16-bit floating-point vector dot product instructions | Alexander Heinecke, Robert Valentine, Mark J. Charney, Raanan Sade, Menachem Adelman +2 more | 2021-06-15 |
| 11023235 | Systems and methods to zero a tile register pair | Raanan Sade, Simon Rubanovich, Amit Gradstein, Alexander Heinecke, Robert Valentine +6 more | 2021-06-01 |
| 11016731 | Using Fuzzy-Jbit location of floating-point multiply-accumulate results | Amit Gradstein, Simon Rubanovich | 2021-05-25 |
| 10990397 | Apparatuses, methods, and systems for transpose instructions of a matrix operations accelerator | Amit Gradstein, Simon Rubanovich, Sagi Meller, Jose Yallouz, Robert Valentine | 2021-04-27 |
| 10963246 | Systems and methods for performing 16-bit floating-point matrix dot product instructions | Alexander Heinecke, Robert Valentine, Mark J. Charney, Raanan Sade, Menachem Adelman +2 more | 2021-03-30 |
| 10942738 | Accelerator systems and methods for matrix operations | Amit Gradstein, Simon Rubanovich, Igor Yanover, Gavri Berger, Eyal Hadas +4 more | 2021-03-09 |
| 10915421 | Technology for dynamically tuning processor features | Adarsh Chauhan, Jayesh Gaur, Franck Sala, Lihu Rappoport, Adi Yoaz +1 more | 2021-02-09 |
| 10877756 | Systems, methods, and apparatuses for tile diagonal | Robert Valentine, Dan Baum, Jesus Corbal, Elmoustapha Ould-Ahmed-Vall, Bret L. Toll +2 more | 2020-12-29 |
| 10866786 | Systems and methods for performing instructions to transpose rectangular tiles | Raanan Sade, Robert Valentine, Mark J. Charney, Simon Rubanovich, Amit Gradstein +5 more | 2020-12-15 |
| 10866807 | Processors, methods, systems, and instructions to generate sequences of integers in numerical order that differ by a constant stride | Elmoustapha Ould-Ahmed-Vall, Seth Abraham, Robert Valentine, Amit Gradstein | 2020-12-15 |
| 10831477 | In-lane vector shuffle instructions | Robert Valentine, Benny Eitan, Doron Orenstein | 2020-11-10 |
| 10824428 | Apparatuses, methods, and systems for hashing instructions | Regev Shemy, Wajdi K. Feghali, Vinodh Gopal, Amit Gradstein, Simon Rubanovich +5 more | 2020-11-03 |
| 10802567 | Performing local power gating in a processor | Nadav Bonen, Ron Gabor, Vjekoslav Svilan, David N. Mackintosh, Jose A. Baiocchi Paredes +2 more | 2020-10-13 |
| 10754655 | Automatic predication of hard-to-predict convergent branches | Adarsh Chauhan, Hong Wang, Jayesh Gaur, Sumeet Bandishte, Lihu Rappoport +4 more | 2020-08-25 |
| 10732970 | Processors, methods, systems, and instructions to generate sequences of integers in which integers in consecutive positions differ by a constant integer stride and where a smallest integer is offset from zero by an integer offset | Seth Abraham, Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Amit Gradstein | 2020-08-04 |
| 10719355 | Criticality based port scheduling | Pooja Roy, Jayesh Gaur, Sreenivas Subramoney, Alexandr Titov, Lihu Rappoport +5 more | 2020-07-21 |
| 10719316 | Apparatus and method of improved packed integer permute instruction | Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal, Bret L. Toll, Mark J. Charney +1 more | 2020-07-21 |
| 10649733 | Multiply add functional unit capable of executing scale, round, getexp, round, getmant, reduce, range and class instructions | Cristina S. Anderson, Simon Rubanovich, Benny Eitan, Amit Gradstein | 2020-05-12 |