Issued Patents All Time
Showing 26–50 of 93 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11061761 | Multichip package link error detection | Robert G. Blankenship, Mahesh Wagh, Zuoguo Wu | 2021-07-13 |
| 10963415 | Bimodal PHY for low latency in high speed interconnects | William R. Halleck, Rahul R. Shah, Eric M. Lee | 2021-03-30 |
| 10931329 | High speed interconnect with channel extension | Rahul R. Shah, William R. Halleck, Fulvio Spagna | 2021-02-23 |
| 10909055 | High performance interconnect physical layer | Darren S. Jue, Robert G. Blankenship, Fulvio Spagna, Ashish Gupta | 2021-02-02 |
| 10868765 | Shaping traffic on PLCA-enabled 10SPE networks | Bernd Sostawa, Martin Miller, Michael Rentschler | 2020-12-15 |
| 10846258 | Voltage modulated control lane | Zuoguo Wu, Mahesh Wagh | 2020-11-24 |
| 10795841 | High performance interconnect physical layer | Darren S. Jue, Sitaraman V. Iyer | 2020-10-06 |
| 10747688 | Low latency retimer | Michelle C. Jen, Debendra Das Sharma, Tao Liang | 2020-08-18 |
| 10712809 | Link power savings with state retention | Naveen Cherukuri, Jeffrey R. Wilcox, Selim Bilgin, David S. Dunning, Robin Tim Frodsham +2 more | 2020-07-14 |
| 10678736 | Extending multichip package link off package | Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Jeff C. Morriss | 2020-06-09 |
| 10606774 | High performance interconnect physical layer | Darren S. Jue, Jeff Willey, Robert G. Blankenship | 2020-03-31 |
| 10599602 | Bimodal phy for low latency in high speed interconnects | William R. Halleck, Rahul R. Shah, Eric M. Lee | 2020-03-24 |
| 10560081 | Method, apparatus, system for centering in a high performance interconnect | Mahesh Wagh, Zuoguo Wu, Gerald Pasdast, Todd Hinck, David M. Lee +1 more | 2020-02-11 |
| 10552253 | Multichip package link error detection | Robert G. Blankenship, Mahesh Wagh, Zuoguo Wu | 2020-02-04 |
| 10461805 | Valid lane training | Lip Khoon Teh, Mahesh Wagh, Zuoguo Wu, Azydee Hamid, Gerald Pasdast | 2019-10-29 |
| 10387339 | High performance interconnect physical layer | Darren S. Jue, Jeff Willey, Robert G. Blankenship | 2019-08-20 |
| 10380046 | High performance interconnect physical layer | Darren S. Jue, Robert G. Blankenship, Fulvio Spagna, Ashish Gupta | 2019-08-13 |
| 10372657 | Bimodal PHY for low latency in high speed interconnects | William R. Halleck, Rahul R. Shah, Eric M. Lee | 2019-08-06 |
| 10324882 | High performance interconnect link state transitions | William R. Halleck, Rahul R. Shah | 2019-06-18 |
| 10277340 | Signal integrity diagnostics for communication channels | Maarten Kuijk | 2019-04-30 |
| 10248591 | High performance interconnect | Robert J. Safranek, Robert G. Blankenship, Jeff Willey, Robert Beers, Darren S. Jue +18 more | 2019-04-02 |
| 10216674 | High performance interconnect physical layer | Darren S. Jue, Sitaraman V. Iyer | 2019-02-26 |
| 10216661 | High performance interconnect physical layer | Darren S. Jue, Rahul C. Shah, Arvind Kumar | 2019-02-26 |
| 10175744 | Link power savings with state retention | Naveen Cherukuri, Jeffrey R. Wilcox, Selim Bilgin, David S. Dunning, Robin Tim Frodsham +2 more | 2019-01-08 |
| 10152446 | Link-physical layer interface adapter | Mahesh Wagh, William R. Halleck, Rahul R. Shah | 2018-12-11 |