Issued Patents All Time
Showing 76–93 of 93 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9229897 | Embedded control channel for high speed serial interconnect | Debendra Das Sharma, Robert G. Blankenship, Darren S. Jue | 2016-01-05 |
| 9208121 | High performance interconnect physical layer | Darren S. Jue, Robert G. Blankenship, Fulvio Spagna, Debendra Das Sharma, Jeffrey C. Swanson | 2015-12-08 |
| 9183171 | Fast deskew when exiting low-power partial-width high speed link state | Debendra Das Sharma, Robert G. Blankenship, Darren S. Jue | 2015-11-10 |
| 9104793 | Method and system of adapting communication links to link conditions on a platform | Arvind Kumar, Santanu Chaudhuri, Darren S. Jue, Dennis R. Halicki | 2015-08-11 |
| 8868955 | Enhanced interconnect link width modulation for power savings | Robert G. Blankenship, Dennis R. Halicki | 2014-10-21 |
| 8831666 | Link power savings with state retention | Naveen Cherukuri, Jeffrey R. Wilcox, Selim Bilgin, David D. Dunning, Robin Tim Frodsham +2 more | 2014-09-09 |
| 8717882 | Repurposing data lane as clock lane by migrating to reduced speed link operation | Robert G. Blankenship, Allen J. Baum | 2014-05-06 |
| 6744810 | Signal repeater for voltage intolerant components used in a serial data line | John T. West | 2004-06-01 |
| 6359951 | Method and apparatus for high speed signaling | Jeffrey C. Morriss | 2002-03-19 |
| 5528762 | Self-timed data streaming receiver and transmitter having reduced latency and increased data streaming capability | — | 1996-06-18 |
| 5133062 | RAM buffer controller for providing simulated first-in-first-out (FIFO) buffers in a random access memory | Sunil Joshi | 1992-07-21 |
| 4949301 | Improved pointer FIFO controller for converting a standard RAM into a simulated dual FIFO by controlling the RAM's address inputs | Sunil Joshi | 1990-08-14 |
| 4785469 | Processor to peripheral interface for asynchronous or synchronous applications | Sunil Joshi | 1988-11-15 |
| 4723243 | CRC calculation machine with variable bit boundary | Sunil Joshi | 1988-02-02 |
| 4720831 | CRC calculation machine with concurrent preset and CRC calculation function | Sunil Joshi | 1988-01-19 |
| 4720830 | CRC calculation apparatus having reduced output bus size | Sunil Joshi | 1988-01-19 |
| 4713605 | Linear feedback shift register for circuit design technology validation | Gil S. Lee | 1987-12-15 |
| 4712215 | CRC calculation machine for separate calculation of checkbits for the header packet and data packet | Sunil Joshi | 1987-12-08 |