Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
TM

Tak M. Mak — 20 Patents

Intel: 17 patents #2,442 of 30,777Top 8%
Globalfoundries: 2 patents #1,397 of 4,424Top 35%
Union City, CA: #76 of 1,177 inventorsTop 7%
California: #29,208 of 386,348 inventorsTop 8%
Overall (All Time): #214,803 of 4,157,543Top 6%
20 Patents All Time
Tak M. Mak has been granted 20 US patents while listed as an inventor at Intel. The first was granted in 1997 and the most recent in January 2023. Tak M. Mak ranks #214,803 of 4,157,543 US inventors in our database (top 5.2%). Patent records list Tak M. Mak in Union City, CA, US.

Patents per Year

Patents granted per year, 1997 to 2023Bar chart with a peak of 4 patents in 2007.peak 41997: 1 patents19972001: 1 patents2002: 1 patents20022003: 1 patents2004: 2 patents20042005: 2 patents2007: 4 patents20072008: 1 patents2014: 1 patents20142015: 2 patents2017: 2 patents20172020: 1 patents2023: 1 patents2023

Issued Patents All Time

Showing 1–20 of 20 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11557420 Coupling inductors in an IC device using interconnecting elements with solder caps and resulting devices Ajit M. Dubey 2023-01-17 $285,462,000
10673723 Systems and methods for dynamically reconfiguring automatic test equipment Louis Yehuda UNGAR, Neil G. Jacobson 2020-06-02
9646758 Method of fabricating integrated circuit (IC) devices Ajit M. Dubey 2017-05-09 $10,322,000
9551741 Current tests for I/O interface connectors Bharani Thiruvengadam, Mladenko Vukic 2017-01-24 $12,666,000
9110134 Input/output delay testing for devices utilizing on-chip delay generation Christopher J. Nelson, David J. Zimmerman, Derek B. Feltham 2015-08-18 $11,320,000
8926196 Method and apparatus for an optical interconnect system Abram M. Detofsky, Chukwunenye S. Nnebe, Jin Yang, Sasha N. Oster 2015-01-06 $26,007,000
8843794 Method, system and apparatus for evaluation of input/output buffer circuitry Christopher J. Nelson, David J. Zimmerman, Pete D. Vogt 2014-09-23 $19,543,000
7373572 System pulse latch and shadow pulse latch coupled to output joining circuit Ming Zhang, Subhasish Mitra, Paul E. Shipley 2008-05-13 $17,373,000
7278074 System and shadow circuits with output joining circuit Subhasish Mitra, Ming Zhang, Quan Shi, Kee Sup Kim 2007-10-02 $20,761,000
7278076 System and scanout circuits with error resilience circuit Ming Zhang, Subhasish Mitra, Victor Zia 2007-10-02 $20,761,000
7188284 Error detecting circuit Subhasish Mitra, Kee Sup Kim, Prashant Goteti 2007-03-06 $17,685,000
7185247 Pseudo bus agent to support functional testing Li Chen 2007-02-27 $10,067,000
6975954 Functional testing of logic circuits that use high-speed links Victor W. Lee 2005-12-13 $11,810,000
6885209 Device testing Michael J. Tripp 2005-04-26 $30,166,000
6757209 Memory cell structural test Michael R. Spica, Michael J. Tripp 2004-06-29 $34,137,000
6721216 Memory addressing structural test Michael R. Spica, Michael J. Tripp 2004-04-13 $35,249,000
6629274 Method and apparatus to structurally detect random defects that impact AC I/O timings in an input/output buffer Mike Tripp, Alper Ilkbahar, R. Tim Frodsham 2003-09-30 $25,999,000
6424926 Bus signature analyzer and behavioral functional test method 2002-07-23 $72,932,000
6222246 Flip-chip having an on-chip decoupling capacitor Paul Winer, Valluri Rao, Richard H. Livengood 2001-04-24 $172,753,000
5621739 Method and apparatus for buffer self-test and characterization Christopher John Sine, Alper Ilkbahar 1997-04-15 $49,693,000