{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Intel", "item": "https://www.patentleaderboard.com/company/intel"}, {"@type": "ListItem", "position": 3, "name": "Kee Sup Kim", "item": "https://www.patentleaderboard.com/inventor/fl:ke_ln:kim-98"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
KK

Kee Sup Kim — 16 Patents

Intel: 11 patents #3,726 of 30,777Top 15%
Samsung: 3 patents #31,179 of 75,807Top 45%
SFSnu R&Db Foundation: 1 patents #423 of 1,470Top 30%
SYSynopsys: 1 patents #1,143 of 2,302Top 50%
Overall (All Time): #284,196 of 4,157,543Top 7%
16 Patents All Time
Kee Sup Kim has been granted 16 US patents while listed as an inventor at Intel. The first was granted in 1996 and the most recent in August 2022. Kee Sup Kim ranks #284,196 of 4,157,543 US inventors in our database (top 6.8%). Patent records list Kee Sup Kim in Hwaseong-si, CA, KR.

Patents per Year

Patents granted per year, 1996 to 2022Bar chart with a peak of 4 patents in 2007.peak 41996: 2 patents19962000: 1 patents20002005: 1 patents20052007: 4 patents20072009: 2 patents20092010: 2 patents20102013: 1 patents20132016: 2 patents20162022: 1 patents2022

Issued Patents All Time

Showing 1–16 of 16 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11403452 Logic yield learning vehicle with phased design windows 2022-08-02 $73,386,000
9524922 Integrated circuit having main route and detour route for signal transmission and integrated circuit package including the same Kyounghwan Lim, Hyoun Soo Park, Bonghyun Lee, Chul Rim, Jungyun Choi +2 more 2016-12-20
9459680 System on chip and temperature control method thereof Hyungock Kim, Wook Kim, Jun Seomun, Chungki Oh, Jaehan Jeon +3 more 2016-10-04
8522188 Method of designing a system-on-chip including a tapless standard cell, designing system and system-on-chip Hyung-Ock Kim, Jae-Han Jeon, Jung Yun CHOI, Hyo-sig Won 2013-08-27
7818642 Hierarchical test response compaction for a plurality of logic blocks Ming Zhang, Avi Kovacs 2010-10-19 $13,567,000
7814383 Compacting circuit responses Subhasish Mitra 2010-10-12
7574640 Compacting circuit responses Subhasish Mitra 2009-08-11 $32,202,000
7523371 System and shadow bistable circuits coupled to output joining circuit Subhasish Mitra, Ming Zhang 2009-04-21 $22,748,000
7278074 System and shadow circuits with output joining circuit Subhasish Mitra, Ming Zhang, Tak M. Mak, Quan Shi 2007-10-02 $20,761,000
7240260 Stimulus generation Subhasish Mitra 2007-07-03 $20,127,000
7188284 Error detecting circuit Subhasish Mitra, Tak M. Mak, Prashant Goteti 2007-03-06 $17,685,000
7185253 Compacting circuit responses Subhasish Mitra 2007-02-27 $10,067,000
6918074 At speed testing asynchronous signals Shyang Su, Adarsh Kalliat, Ajith Prasad 2005-07-12 $27,947,000
6076173 Architectural coverage measure Rathish Jayabharathi, Saviz Artang 2000-06-13 $267,683,000
5574733 Scan-based built-in self test (BIST) with automatic reseeding of pattern generator 1996-11-12 $38,860,000
5504756 Method and apparatus for multi-frequency, multi-phase scan chain Leonard Joshua Schultz 1996-04-02 $107,023,000