Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11403452 | Logic yield learning vehicle with phased design windows | — | 2022-08-02 |
| 9524922 | Integrated circuit having main route and detour route for signal transmission and integrated circuit package including the same | Kyounghwan Lim, Hyoun Soo Park, Bonghyun Lee, Chul Rim, Jungyun Choi +2 more | 2016-12-20 |
| 9459680 | System on chip and temperature control method thereof | Hyungock Kim, Wook Kim, Jun Seomun, Chungki Oh, Jaehan Jeon +3 more | 2016-10-04 |
| 8522188 | Method of designing a system-on-chip including a tapless standard cell, designing system and system-on-chip | Hyung-Ock Kim, Jae-Han Jeon, Jung Yun CHOI, Hyo-sig Won | 2013-08-27 |
| 7818642 | Hierarchical test response compaction for a plurality of logic blocks | Ming Zhang, Avi Kovacs | 2010-10-19 |
| 7814383 | Compacting circuit responses | Subhasish Mitra | 2010-10-12 |
| 7574640 | Compacting circuit responses | Subhasish Mitra | 2009-08-11 |
| 7523371 | System and shadow bistable circuits coupled to output joining circuit | Subhasish Mitra, Ming Zhang | 2009-04-21 |
| 7278074 | System and shadow circuits with output joining circuit | Subhasish Mitra, Ming Zhang, Tak M. Mak, Quan Shi | 2007-10-02 |
| 7240260 | Stimulus generation | Subhasish Mitra | 2007-07-03 |
| 7188284 | Error detecting circuit | Subhasish Mitra, Tak M. Mak, Prashant Goteti | 2007-03-06 |
| 7185253 | Compacting circuit responses | Subhasish Mitra | 2007-02-27 |
| 6918074 | At speed testing asynchronous signals | Shyang Su, Adarsh Kalliat, Ajith Prasad | 2005-07-12 |
| 6076173 | Architectural coverage measure | Rathish Jayabharathi, Saviz Artang | 2000-06-13 |
| 5574733 | Scan-based built-in self test (BIST) with automatic reseeding of pattern generator | — | 1996-11-12 |
| 5504756 | Method and apparatus for multi-frequency, multi-phase scan chain | Leonard Joshua Schultz | 1996-04-02 |