Issued Patents All Time
Showing 101–125 of 132 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6122714 | Order supporting mechanisms for use in a switch-based multi-processor system | Stephen R. VanDoren, Madhumitra Sharma, David Fenwick | 2000-09-19 |
| 6108737 | Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system | Madhumitra Sharma, Stephen R. Van Doren, Kourosh Gharachorloo | 2000-08-22 |
| 6105108 | Method and apparatus for releasing victim data buffers of computer systems by comparing a probe counter with a service counter | Stephen R. Van Doren | 2000-08-15 |
| 6101420 | Method and apparatus for disambiguating change-to-dirty commands in a switch based multi-processing system with coarse directories | Stephen R. VanDoren, Madhumitra Sharma, Kourosh Gharachorloo | 2000-08-08 |
| 6101581 | Separate victim buffer read and release control | Stephen Doren, Robert Eugene Stewart, James B. Keller | 2000-08-08 |
| 6088771 | Mechanism for reducing latency of memory barrier operations on a multiprocessor system | Madhumitra Sharma, Kourosh Gharachorloo, Stephen R. Van Doren | 2000-07-11 |
| 6085263 | Method and apparatus for employing commit-signals and prefetching to maintain inter-reference ordering in a high-performance I/O processor | Madhumitra Sharma, Chester Pawlowski, Kourosh Gharachorloo, Stephen R. Van Doren | 2000-07-04 |
| 6081887 | System for passing an index value with each prediction in forward direction to enable truth predictor to associate truth value with particular branch instruction | Edward J. McLellan, Joel S. Emer | 2000-06-27 |
| 6061765 | Independent victim data buffer and probe buffer release control utilzing control flag | Stephen R. Van Doren, Robert Eugene Stewart, James B. Keller | 2000-05-09 |
| 6055605 | Technique for reducing latency of inter-reference ordering using commit signals in a multiprocessor system having shared caches | Madhumitra Sharma, Kourosh Gharachorloo, Stephen R. Van Doren | 2000-04-25 |
| 6049889 | High performance recoverable communication method and apparatus for write-only networks | Glenn P. Garvey, Richard B. Gillett, Jr. | 2000-04-11 |
| 6014690 | Employing multiple channels for deadlock avoidance in a cache coherency protocol | Stephen R. VanDoren, Madhumitra Sharma | 2000-01-11 |
| 5966737 | Apparatus and method for serialized set prediction | Joseph Macri | 1999-10-12 |
| 5953747 | Apparatus and method for serialized set prediction | Joseph Macri | 1999-09-14 |
| 5933860 | Multiprobe instruction cache with instruction-based probe hint generation and training whereby the cache bank or way to be accessed next is predicted | Joel S. Emer, Edward J. McLellan | 1999-08-03 |
| 5829051 | Apparatus and method for intelligent multiple-probe cache allocation | Richard B. Gillett, Jr., Tryggve Fossum | 1998-10-27 |
| 5828874 | Past-history filtered branch prediction | David J. Sager | 1998-10-27 |
| 5758142 | Trainable apparatus for predicting instruction outcomes in pipelined processors | Scott McFarling, Joel S. Emer, Edward J. McLellan | 1998-05-26 |
| 5619662 | Memory reference tagging | David J. Sager, David B. Fite, Jr. | 1997-04-08 |
| 5581719 | Multiple block line prediction | David J. Sager | 1996-12-03 |
| 5564118 | Past-history filtered branch prediction | David J. Sager, William B. Noyce | 1996-10-08 |
| 5551048 | Ring based distributed communication bus for a multiprocessor network | — | 1996-08-27 |
| 5519841 | Multi instruction register mapper | David J. Sager, David B. Fite, Jr. | 1996-05-21 |
| 5509135 | Multi-index multi-way set-associative cache | — | 1996-04-16 |
| 5283873 | Next line prediction apparatus for a pipelined computed system | David J. Sager | 1994-02-01 |