Issued Patents All Time
Showing 126–132 of 132 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5235697 | Set prediction cache memory system using bits of the main memory address | John H. Zurawski | 1993-08-10 |
| 5214770 | System for flushing instruction-cache only when instruction-cache address and data-cache address are matched and the execution of a return-from-exception-or-interrupt command | Raj K. Ramanujan, Peter J. Bannon | 1993-05-25 |
| 5197132 | Register mapping system having a log containing sequential listing of registers that were changed in preceding cycles for precise post-branch recovery | David J. Sager | 1993-03-23 |
| 5179673 | Subroutine return prediction mechanism using ring buffer and comparing predicated address with actual address to validate or flush the pipeline | David J. Sager | 1993-01-12 |
| 5038278 | Cache with at least two fill rates | Raj K. Ramanujan, Peter J. Bannon, Walter A. Beach | 1991-08-06 |
| 5003459 | Cache memory system | Raj K. Ramanujan, Peter J. Bannon, David J. Sager | 1991-03-26 |
| 4490784 | High-speed data transfer unit for digital data processing system | David Curtis Ives, David Kyle Miller | 1984-12-25 |