Issued Patents All Time
Showing 76–100 of 132 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7395374 | System and method for conflict responses in a cache coherency protocol with ordering point migration | Gregory Edward Tierney, Stephen R. Van Doren | 2008-07-01 |
| 7383409 | Cache systems and methods for employing speculative fills | Gregory Edward Tierney | 2008-06-03 |
| 7380107 | Multi-processor system utilizing concurrent speculative source request and system source request in response to cache miss | Gregory Edward Tierney, Stephen R. Van Doren | 2008-05-27 |
| 7376794 | Coherent signal in a multi-processor system | Gregory Edward Tierney, Stephen R. Van Doren | 2008-05-20 |
| 7360069 | Systems and methods for executing across at least one memory barrier employing speculative fills | Gregory Edward Tierney | 2008-04-15 |
| 7340565 | Source request arbitration | Gregory Edward Tierney | 2008-03-04 |
| 7240165 | System and method for providing parallel data requests | Gregory Edward Tierney | 2007-07-03 |
| 7237067 | Managing a multi-way associative cache | — | 2007-06-26 |
| 7177987 | System and method for responses between different cache coherency protocols | Stephen R. Van Doren, Gregory Edward Tierney | 2007-02-13 |
| 7149852 | System and method for blocking data responses | Stephen R. Van Doren, Gregory Edward Tierney | 2006-12-12 |
| 7143245 | System and method for read migratory optimization in a cache coherency protocol | Gregory Edward Tierney, Stephen R. Van Doren | 2006-11-28 |
| 6961825 | Cache coherency mechanism using arbitration masks | Stephen R. Van Doren, Madhumitra Sharma | 2005-11-01 |
| 6904465 | Low latency inter-reference ordering in a multiple processor system employing a multiple-level inter-node switch | Madhumitra Sharma, Stephen R. Van Doren | 2005-06-07 |
| 6801986 | Livelock prevention by delaying surrender of ownership upon intervening ownership request during load locked / store conditional atomic memory operation | Stephen R. Van Doren, Madhumitra Sharma | 2004-10-05 |
| 6769057 | System and method for determining operand access to data | — | 2004-07-27 |
| 6647466 | Method and apparatus for adaptively bypassing one or more levels of a cache hierarchy | — | 2003-11-11 |
| 6636948 | Method and system for a processor to gain assured ownership of an up-to-date copy of data | Stephen R. Van Doren, Madhu Sharna | 2003-10-21 |
| 6493801 | Adaptive dirty-block purging | Nikolaos Hardavellas | 2002-12-10 |
| 6295585 | High-performance communication method and apparatus for write-only networks | Richard B. Gillett, Jr., Glenn P. Garvey | 2001-09-25 |
| 6286090 | Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetches | Madhumitra Sharma, Stephen R. Van Doren, Kourosh Gharachorloo | 2001-09-04 |
| 6279084 | Shadow commands to optimize sequencing of requests in a switch-based multi-processor system | Stephen R. VanDoren, Madhumitra Sharma, Hari K. Nagpal | 2001-08-21 |
| 6249520 | High-performance non-blocking switch with multiple channel ordering constraints | Stephen R. VanDoren, Madhumitra Sharma, Craig D. Keefer, David Wayne Davis | 2001-06-19 |
| 6209065 | Mechanism for optimizing generation of commit-signals in a distributed shared-memory system | Stephen R. Van Doren, Kourosh Gharachorloo, Madhumitra Sharma | 2001-03-27 |
| 6202126 | Victimization of clean data blocks | Stephen R. Van Doren, Madhumitra Sharma | 2001-03-13 |
| 6154816 | Low occupancy protocol for managing concurrent transactions with dependencies | Madhumitra Sharma, Stephen R. VanDoren | 2000-11-28 |