Issued Patents All Time
Showing 51–75 of 132 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9251073 | Update mask for handling interaction between fills and updates | William C. Hasenplaugh | 2016-02-02 |
| 9201792 | Short circuit of probes in a chain | Samantika Subramaniam, William C. Hasenplaugh, Joel S. Emer | 2015-12-01 |
| 9146871 | Retrieval of previously accessed data in a multi-core processor | William C. Hasenplaugh, Joel S. Emer | 2015-09-29 |
| 9037804 | Efficient support of sparse data structure access | William C. Hasenplaugh, Joel S. Emer | 2015-05-19 |
| 8806147 | System and method for creating ordering points | Gregory Edward Tierney, St phen R. Van Doren | 2014-08-12 |
| 8769201 | Technique for controlling computing resources | William C. Hasenplaugh, Joel S. Emer, Tryggve Fossum, Aamer Jaleel | 2014-07-01 |
| 8769209 | Method and apparatus for achieving non-inclusive cache performance with inclusive caches | Aamer Jaleel, Eric R. Borch, Malini K. Bhandaru, Joel S. Emer | 2014-07-01 |
| 8533422 | Instruction prefetching using cache line history | Samantika Subramaniam, Aamer Jaleel | 2013-09-10 |
| 8468308 | System and method for non-migratory requests in a cache coherency protocol | Stephen R. Van Doren, Gregory Edward Tierney | 2013-06-18 |
| 8438335 | Probe speculative address file | William C. Hasenplaugh | 2013-05-07 |
| 8407421 | Cache spill management techniques using cache spill prediction | William C. Hasenplaugh, Aamer Jaleel, George Z. Chrysos | 2013-03-26 |
| 8301844 | Consistency evaluation of program execution across at least one memory barrier | Gregory Edward Tierney | 2012-10-30 |
| 8281079 | Multi-processor system receiving input from a pre-fetch buffer | Gregory Edward Tierney | 2012-10-02 |
| 8176259 | System and method for resolving transactions in a cache coherency protocol | Stephen R. Van Doren, Gregory Edward Tierney | 2012-05-08 |
| 8145847 | Cache coherency protocol with ordering points | Stephen R. Van Doren, Gregory Edward Tierney | 2012-03-27 |
| 8090914 | System and method for creating ordering points | Gregory Edward Tierney, Stephen R. Van Doren | 2012-01-03 |
| 7962696 | System and method for updating owner predictors | Gregory Edward Tierney | 2011-06-14 |
| 7856534 | Transaction references for requests in a multi-processor network | Stephen R. Van Doren, Gregory Edward Tierney | 2010-12-21 |
| 7818391 | System and method to facilitate ordering point migration | Stephen R. Van Doren, Gregory Edward Tierney | 2010-10-19 |
| 7769959 | System and method to facilitate ordering point migration to memory | Stephen R. Van Doren, Gregory Edward Tierney | 2010-08-03 |
| 7725657 | Dynamic quality of service (QoS) for a shared cache | William C. Hasenplaugh, Li Zhao, Ravishankar Iyer, Ramesh Illikkal, Srihari Makineni +2 more | 2010-05-25 |
| 7620696 | System and method for conflict responses in a cache coherency protocol | Stephen R. Van Doren, Gregory Edward Tierney | 2009-11-17 |
| 7409503 | Register file systems and methods for employing speculative fills | Gregory Edward Tierney | 2008-08-05 |
| 7409500 | Systems and methods for employing speculative fills | Gregory Edward Tierney | 2008-08-05 |
| 7406565 | Multi-processor systems and methods for backup for non-coherent speculative fills | Gregory Edward Tierney | 2008-07-29 |