Issued Patents All Time
Showing 26–50 of 132 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10469397 | Processors and methods with configurable network-based dataflow operator circuits | Kermin Fleming, Kent D. Glossop | 2019-11-05 |
| 10445098 | Processors and methods for privileged configuration in a spatial array | Kermin Fleming, Kent D. Glossop | 2019-10-15 |
| 10445250 | Apparatus, methods, and systems with a configurable spatial accelerator | Kermin Fleming, Kent D. Glossop | 2019-10-15 |
| 10445234 | Processors, methods, and systems for a configurable spatial accelerator with transactional and replay features | Kermin Fleming, Kent D. Glossop, Samantika S. Sury | 2019-10-15 |
| 10445451 | Processors, methods, and systems for a configurable spatial accelerator with performance, correctness, and power reduction features | Kermin Fleming, Kent D. Glossop, Ping T. Tang | 2019-10-15 |
| 10430252 | Synchronization logic for memory requests | Samantika S. Sury, Robert G. Blankenship | 2019-10-01 |
| 10416999 | Processors, methods, and systems with a configurable spatial accelerator | Kermin Fleming, Kent D. Glossop | 2019-09-17 |
| 10417175 | Apparatus, methods, and systems for memory consistency in a configurable spatial accelerator | Kermin Fleming, Kent D. Glossop | 2019-09-17 |
| 10402168 | Low energy consumption mantissa multiplication for floating point multiply-add operations | William C. Hasenplaugh, Kermin Fleming, Tryggve Fossum | 2019-09-03 |
| 10402176 | Methods and apparatus to compile code to generate data flow code | Kent D. Glossop, Kermin Fleming, Yongzhi Zhang, Jim Sukha, Uma Srinivasan | 2019-09-03 |
| 10387319 | Processors, methods, and systems for a configurable spatial accelerator with memory system performance, power reduction, and atomics support features | Michael C. Adler, Chiachen Chou, Neal C. Crago, Kermin Fleming, Kent D. Glossop +3 more | 2019-08-20 |
| 10379855 | Processors, methods, systems, and instructions to load multiple data elements to destination storage locations other than packed data registers | William C. Hasenplaugh, Chris J. Newburn, Samantika S. Sury | 2019-08-13 |
| 10380063 | Processors, methods, and systems with a configurable spatial accelerator having a sequencer dataflow operator | JINJIE TANG, Kermin Fleming, Kent D. Glossop, Jim Sukha | 2019-08-13 |
| 10275243 | Interruptible and restartable matrix multiplication instructions, processors, methods, and systems | Edward T. Grochowski, Asit K. Mishra, Robert Valentine, Mark J. Charney | 2019-04-30 |
| 10146690 | Synchronization logic for memory requests | Samantika S. Sury, Robert G. Blankenship | 2018-12-04 |
| 10102124 | High bandwidth full-block write commands | William C. Hasenplaugh, Joel S. Emer, Samantika Subramaniam | 2018-10-16 |
| 9934146 | Hardware apparatuses and methods to control cache line coherency | Samantika S. Sury, William C. Hasenplaugh | 2018-04-03 |
| 9898408 | Sharing aware snoop filter apparatus and method | Samantika S. Sury, Robert G. Blankenship | 2018-02-20 |
| 9740617 | Hardware apparatuses and methods to control cache line coherence | Samantika S. Sury, William C. Hasenplaugh, Joel S. Emer, David A. Webb | 2017-08-22 |
| 9734069 | Multicast tree-based data distribution in distributed shared cache | William C. Hasenplaugh, Samantika S. Sury | 2017-08-15 |
| 9727482 | Address range priority mechanism | Samantika S. Sury, William C. Hasenplaugh | 2017-08-08 |
| 9588889 | Domain state | William C. Hasenplaugh, Joel S. Emer | 2017-03-07 |
| 9477610 | Address range priority mechanism | Samantika Subramaniam, William C. Hasenplaugh | 2016-10-25 |
| 9418016 | Method and apparatus for optimizing the usage of cache memories | Joel S. Emer, William C. Hasenplaugh | 2016-08-16 |
| 9262327 | Signature based hit-predicting cache | William C. Hasenplaugh, Aamer Jaleel, Joel S. Emer, Carole-Jean Wu | 2016-02-16 |