Issued Patents All Time
Showing 51–74 of 74 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7038505 | Configurable enabling pulse clock generation for multiple signaling modes | Ying Cole, Songmin Kim | 2006-05-02 |
| 7013406 | Method and apparatus to dynamically change an operating frequency and operating voltage of an electronic device | Alon Naveh, Roman Surgutchik, Stephen H. Gunther, Hung-Piao Ma, Kevin Dai +1 more | 2006-03-14 |
| 6957352 | Processor temperature control interface | Benson D. Inkley, Nathan Schultz | 2005-10-18 |
| 6924710 | Voltage ID based frequency control for clock generating circuit | Keng L. Wong, Hong-Piao Ma, Greg Taylor, Chee How Lim, Edward A. Burton +1 more | 2005-08-02 |
| 6907487 | Enhanced highly pipelined bus architecture | Gurbir Singh, Stephen S. Pawlowski, David L. Hill, Donald D. Parker | 2005-06-14 |
| 6880076 | System and method for communicating device information between a device and a controller | Matthew M. Ma, Edward P. Osburn, Michael A. Stapleton | 2005-04-12 |
| 6880031 | Snoop phase in a highly pipelined bus architecture | Gurbir Singh, Stephen S. Pawlowski, David L. Hill, Donald D. Parker | 2005-04-12 |
| 6809606 | Voltage ID based frequency control for clock generating circuit | Keng L. Wong, Hong-Piao Ma, Greg Taylor, Chee How Lim, Edward A. Burton +1 more | 2004-10-26 |
| 6807592 | Quad pumped bus architecture and protocol | Gurbir Singh, Stephen S. Pawlowski, David L. Hill, Donald D. Parker | 2004-10-19 |
| 6804735 | Response and data phases in a highly pipelined bus architecture | Gurbir Singh, Stephen S. Pawlowski, David L. Hill, Donald D. Parker | 2004-10-12 |
| 6742160 | Checkerboard parity techniques for a multi-pumped bus | — | 2004-05-25 |
| 6732242 | External bus transaction scheduling system | David L. Hill, Paul Breuder, Derek T. Bachand | 2004-05-04 |
| 6708269 | Method and apparatus for multi-mode fencing in a microprocessor system | Keshavan Tiruvallur, Douglas M. Carmean, Muntaquim Chowdhury, Madhavan Parthasarathy | 2004-03-16 |
| 6662173 | Access control of a resource shared between components | Per Hammarlund | 2003-12-09 |
| 6609171 | Quad pumped bus architecture and protocol | Gurbir Singh, Stephen S. Pawlowski, David L. Hill, Donald D. Parker | 2003-08-19 |
| 6601121 | Quad pumped bus architecture and protocol | Gurbir Singh, Stephen S. Pawlowski, David L. Hill, Donald D. Parker | 2003-07-29 |
| 6591319 | Glitch protection and detection for strobed data | Nasser A. Kurd | 2003-07-08 |
| 6505262 | Glitch protection and detection for strobed data | Nasser A. Kurd | 2003-01-07 |
| 6463494 | Method and system for implementing control signals on a low pin count bus | Jeff C. Morriss, Pranav Mehta, Narayanan Iyer, Peter J. Ruscito, Shreekant S. Thakkar | 2002-10-08 |
| 6446154 | Method and mechanism for virtualizing legacy sideband signals in a hub interface architecture | Jasmin Ajanovic, Stephen S. Pawlowski | 2002-09-03 |
| 6434650 | Apparatus and method for multiplexing bi-directional data onto a low pin count bus between a host CPU and co-processor | Jeff C. Morris, Narayana Iyer, Pranav Mehta, Shreekant S. Thakkar, Peter J. Ruscito | 2002-08-13 |
| 6216208 | Prefetch queue responsive to read request sequences | David L. Hill, Chinna Prudvi, Derek T. Bachand, Matthew A. Fisch | 2001-04-10 |
| 5560029 | Data processing system with synchronization coprocessor for multiple threads | Gregory M. Papadopoulos, Rishiyur S. Nikhil | 1996-09-24 |
| 5430850 | Data processing system with synchronization coprocessor for multiple threads | Gregory M. Papadopoulos, Rishiyur S. Nikhil | 1995-07-04 |