KW

Keng L. Wong

IN Intel: 56 patents #541 of 30,777Top 2%
AT Ap Memory Technology: 3 patents #6 of 16Top 40%
SM Sunhing Millennium: 3 patents #7 of 20Top 35%
Overall (All Time): #35,557 of 4,157,543Top 1%
63
Patents All Time

Issued Patents All Time

Showing 25 most recent of 63 patents

Patent #TitleCo-InventorsDate
12394473 Interface of a memory circuit Wenliang Chen, Girish Nanjappa, Lin Ma, Hung-Piao Ma, Chun-Yi Lin 2025-08-19
11967363 Display controller having a surge protection unit and display system thereof Wenliang Chen, Girish Nanjappa, Lin Ma, Hung-Piao Ma, Chun-Yi Lin 2024-04-23
11842763 Interface of a memory circuit and memory system thereof Wenliang Chen, Girish Nanjappa, Lin Ma, Hung-Piao Ma, Chun-Yi Lin 2023-12-12
11757432 Device and method of correcting duty cycle Xuan Zhang, Po-Han Chen, Alessandro Minzoni 2023-09-12
7498892 Split-biased interpolated voltage-controlled oscillator and phase locked loop Mingwei Huang, David E. Duarte, Shuching Hsu 2009-03-03
7408420 Multi mode clock generator Feng Wang 2008-08-05
7404099 Phase-locked loop having dynamically adjustable up/down pulse widths Mingwei Huang, Raymond (Hon-Mo) Law, Chi-Yeu Chao 2008-07-22
7386749 Controlling sequence of clock distribution to clock distribution domains Michael C. Rifani, Vaughn J. Grossnickle 2008-06-10
7310020 Self-biased phased-locked loop Swee Boon Tan 2007-12-18
7308372 Phase jitter measurement circuit Michael C. Rifani, Christopher Chun-Ning Pan 2007-12-11
7242261 Voltage control for clock generating circuit Hong-Piao Ma, Greg Taylor 2007-07-10
7237128 Method and apparatus to dynamically change an operating frequency and operating voltage of an electronic device Alon Naveh, Roman Surgutchik, Stephen H. Gunther, Robert Greiner, Hung-Piao Ma +1 more 2007-06-26
7199624 Phase locked loop system capable of deskewing Gregory F. Taylor, Chee How Lim 2007-04-03
7197659 Global I/O timing adjustment using calibrated delay elements Chee How Lim, Songmin Kim 2007-03-27
7184503 Multi-loop circuit capable of providing a delayed clock in phase locked loops Chee How Lim 2007-02-27
7173461 Self-biased phased-locked loop Swee Boon Tan 2007-02-06
7154320 Frequency-based slope-adjustment circuit Usman Mughal 2006-12-26
7024324 Delay element calibration Michael C. Rifani, Christopher Chun-Ning Pan 2006-04-04
7023945 Method and apparatus for jitter reduction in phase locked loops Chee How Lim 2006-04-04
7013406 Method and apparatus to dynamically change an operating frequency and operating voltage of an electronic device Alon Naveh, Roman Surgutchik, Stephen H. Gunther, Robert Greiner, Hung-Piao Ma +1 more 2006-03-14
6985041 Clock generating circuit and method Niraj Bindal, Hong-Piao Ma, George L. Geannopoulos, Greg Taylor, Edward A. Burton 2006-01-10
6937075 Method and apparatus for reducing lock time in dual charge-pump phase-locked loops Chee How Lim, Rachael Parker 2005-08-30
6934872 Method and apparatus for optimizing clock distribution to reduce the effect of power supply noise Hung-Piao Ma, Tawfik M. Rahal-Arabi, Javed S. Barkatullah, Edward A. Burton 2005-08-23
6924710 Voltage ID based frequency control for clock generating circuit Hong-Piao Ma, Greg Taylor, Chee How Lim, Robert Greiner, Edward A. Burton +1 more 2005-08-02
6919769 Method and apparatus for fast lock acquisition in self-biased phase locked loops Chee How Lim 2005-07-19