Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11461504 | Apparatus for autonomous security and functional safety of clock and voltages including adjustment of a divider ratio | Nasser A. Kurd, Praveen Mosalikanti, Thripthi Hegde, Mark L. Neidengard, Qi Wang +1 more | 2022-10-04 |
| 11211934 | Apparatus to improve lock time of a frequency locked loop | Praveen Mosalikanti, Qi Wang, Mark L. Neidengard, Nasser A. Kurd | 2021-12-28 |
| 11048284 | Self-referenced droop detector circuitry | Praveen Mosalikanti, Gerhard Schrom, Nasser A. Kurd | 2021-06-29 |
| 10824764 | Apparatus for autonomous security and functional safety of clock and voltages | Nasser A. Kurd, Praveen Mosalikanti, Thripthi Hegde, Mark L. Neidengard, Qi Wang +1 more | 2020-11-03 |
| 10790832 | Apparatus to improve lock time of a frequency locked loop | Praveen Mosalikanti, Qi Wang, Mark L. Neidengard, Nasser A. Kurd | 2020-09-29 |
| 10790838 | Method and apparatus to perform dynamic frequency scaling while a phase-locked loop operates in a closed loop | Praveen Mosalikanti, Syed Feruz Syed Farooq, Mark L. Neidengard, Nasser A. Kurd | 2020-09-29 |
| 10614774 | Device, method and system for on-chip generation of a reference clock signal | Nasser A. Kurd, Daniel J. Ragland, Ameya Ambardekar, John Fallin, Praveen Mosalikanti | 2020-04-07 |
| 10423182 | Self-referenced droop detector circuitry | Praveen Mosalikanti, Gerhard Schrom, Nasser A. Kurd | 2019-09-24 |
| 9876491 | Apparatus, system, and method for re-synthesizing a clock signal | Mark L. Neidengard, Nasser A. Kurd, Jeffrey Krieger | 2018-01-23 |
| 9836078 | Clock generation system with dynamic distribution bypass mode | Allan Feldman, Nasser A. Kurd, Mark L. Neidengard, Praveen Mosalikanti | 2017-12-05 |
| 9450589 | Clock generation system with dynamic distribution bypass mode | Allan Feldman, Nasser A. Kurd, Mark L. Neidengard, Praveen Mosalikanti | 2016-09-20 |
| 9190991 | Apparatus, system, and method for re-synthesizing a clock signal | Mark L. Neidengard, Nasser A. Kurd, Jeffrey Krieger | 2015-11-17 |
| 8878579 | System and method for scaling power of a phase-locked loop architecture | Nasser A. Kurd | 2014-11-04 |
| 8756451 | Frequency synthesis methods and systems | Mark L. Neidengard, Nasser A. Kurd, Robert Greiner | 2014-06-17 |
| 7386749 | Controlling sequence of clock distribution to clock distribution domains | Michael C. Rifani, Keng L. Wong | 2008-06-10 |
| 6433624 | Threshold voltage generation circuit | Siva G. Narendra, Vivek K. De | 2002-08-13 |
| 6346803 | Current reference | Siva G. Narendra, Vivek K. De | 2002-02-12 |