Issued Patents All Time
Showing 51–63 of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5726995 | Method and apparatus for selecting modes of an intergrated circuit | — | 1998-03-10 |
| 5712826 | Apparatus and a method for embedding dynamic state machines in a static environment | Roshan Fernando | 1998-01-27 |
| 5696953 | Method and apparatus for power management of an integrated circuit | Kelly Fitzpatrick, Jeffrey E. Smith | 1997-12-09 |
| 5630107 | System for loading PLL from bus fraction register when bus fraction register is in either first or second state and bus unit not busy | Douglas M. Carmean, Kathakali Debnath, Roshan Fernando, Robert F. Krick | 1997-05-13 |
| 5592111 | Clock speed limiter for an integrated circuit | Alexander Waizman, Bart R. McDaniel | 1997-01-07 |
| 5586307 | Method and apparatus supplying synchronous clock signals to circuit components | Kelly Fitzpatrick, Jeffrey E. Smith | 1996-12-17 |
| 5557225 | Pulsed flip-flop circuit | Martin S. Denham, Jeffrey E. Smith, Roshan Fernando | 1996-09-17 |
| 5446867 | Microprocessor PLL clock circuit with selectable delayed feedback | Ian A. Young, Jeffrey E. Smith | 1995-08-29 |
| 5425074 | Fast programmable/resettable CMOS Johnson counters | — | 1995-06-13 |
| 5412349 | PLL clock generator integrated with microprocessor | Ian A. Young, Jeffrey K. Greason | 1995-05-02 |
| 5280605 | Clock speed limiter for microprocessor | Ian A. Young | 1994-01-18 |
| 5274337 | Clock speed limiter for a microprocessor by comparing clock signal with a predetermined frequency | Ian A. Young | 1993-12-28 |
| 5111067 | Power up reset circuit | Joseph D. Schutz | 1992-05-05 |