KD

Kathakali Debnath

IN Intel: 2 patents #13,213 of 30,777Top 45%
📍 Beaverton, OR: #1,624 of 3,140 inventorsTop 55%
🗺 Oregon: #12,654 of 28,073 inventorsTop 50%
Overall (All Time): #2,270,310 of 4,157,543Top 55%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
5666537 Power down scheme for idle processor components Anurag Sah, Cong Q. Khieu 1997-09-09
5630107 System for loading PLL from bus fraction register when bus fraction register is in either first or second state and bus unit not busy Douglas M. Carmean, Roshan Fernando, Robert F. Krick, Keng L. Wong 1997-05-13