MY

Myung Jin Yim

IN Intel: 10 patents #4,046 of 30,777Top 15%
KAIST: 7 patents #1,829 of 11,619Top 20%
Micron: 7 patents #1,853 of 6,345Top 30%
Globalfoundries: 2 patents #1,397 of 4,424Top 35%
Overall (All Time): #143,839 of 4,157,543Top 4%
27
Patents All Time

Issued Patents All Time

Showing 25 most recent of 27 patents

Patent #TitleCo-InventorsDate
12078853 Semiconductor package with embedded optical die Vivek Raghunathan 2024-09-03
11982854 Co-packaging with silicon photonics hybrid planar lightwave circuit Sang Yup Kim, Woosung Kim 2024-05-14
11531174 Co-packaging with silicon photonics hybrid planar lightwave circuit Sang Yup Kim, Woosung Kim 2022-12-20
11156788 Semiconductor package with embedded optical die Vivek Raghunathan 2021-10-26
10953593 Molding compound including a carbon nano-tube dispersion Jason M. Brand 2021-03-23
10727368 Optoelectronic device module having a silicon interposer Seungjae Lee, Sandeep Razdan 2020-07-28
10347615 Method of fabricating an optical module that includes an electronic package Jay Lee, Jong-Min Hong 2019-07-09
10242976 In-package photonics integration and assembly architecture 2019-03-26
10014654 Optoelectronic packaging assemblies Ansheng Liu, Valentin Yepanechnikov 2018-07-03
9950464 Forming a carbon nano-tube dispersion Jason M. Brand 2018-04-24
9900102 Integrated circuit with chip-on-chip and chip-on-substrate configuration Olufemi I. Dosunmu, Ansheng Liu 2018-02-20
9893816 Dynamic beam steering optoelectronic packages Woosung Kim 2018-02-13
9374902 Package including an underfill material in a portion of an area between the package and a substrate or another package Nanette Quevedo, Richard Strode 2016-06-21
9041228 Molding compound including a carbon nano-tube dispersion Jason M. Brand 2015-05-26
8653675 Package including at least one topological feature on an encapsulant material to resist out-of-plane deformation James Zhang, Jason M. Brand, Jacob Brooksby, Dejen Eshete, Ravikumar Adimula +1 more 2014-02-18
8451620 Package including an underfill material in a portion of an area between the package and a substrate or another package Nanette Quevedo, Richard Strode 2013-05-28
8409927 Methods for fabricating integrated circuit systems including high reliability die under-fill 2013-04-02
8383460 Method for fabricating through substrate vias in semiconductor substrate 2013-02-26
8344491 Multi-die building block for stacked-die package Ravikumar Adimula 2013-01-01
7446384 CMOS image sensor module with wafers Kyung Wook Paik, Ho Young SON, Yong Min KWON 2008-11-04
7081675 Multilayered anisotropic conductive adhesive for fine pitch Jun Sang Hwang 2006-07-25
6930399 High reliability non-conductive adhesives for non-solder flip chip bondings and flip chip bonding method using the same Kyung Wook Paik 2005-08-16
6878435 High adhesion triple layered anisotropic conductive adhesive film Kyung Wook Paik 2005-04-12
6518097 Method for fabricating wafer-level flip chip package using pre-coated anisotropic conductive adhesive Kyung Wook Baik 2003-02-11
6514560 Method for manufacturing conductive adhesive for high frequency flip chip package applications Kyung Wook Paik, Woon-Seong Kwon 2003-02-04