Issued Patents All Time
Showing 76–100 of 115 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9335814 | Adaptively controlling low power mode operation for a cache memory | Stefan Rusu, Min Huang, Wei-Chih Chen | 2016-05-10 |
| 9317389 | Apparatus and method for controlling the reliability stress rate on a processor | Dorit Shapira, Efraim Rotem, Nadav Shulman, Shmulik Zobel, Allen W. Chu | 2016-04-19 |
| 9292468 | Performing frequency coordination in a multiprocessor system based on response timing optimization | Ankush Varma | 2016-03-22 |
| 9268393 | Enforcing a power consumption duty cycle in a processor | Ankush Varma, Martin T. Rowland, Brian J. Griffith, Viktor D. Vogman, Joseph R. Doucette +6 more | 2016-02-23 |
| 9170624 | User level control of power management policies | Jeremy J. Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh, Eliezer Weissmann +7 more | 2015-10-27 |
| 9158351 | Dynamic power limit sharing in a platform | Ankush Varma, Cesar A. Quiroz, Vivek Garg, Martin T. Rowland, Inder M. Sodhi +1 more | 2015-10-13 |
| 9141166 | Method, apparatus, and system for energy efficiency and energy conservation including dynamic control of energy consumption in power domains | Martin T. Rowland, Cesar A. Quiroz, Joseph R. Doucette, Gopikrishna Jandhyala, Kai Cheng +2 more | 2015-09-22 |
| 9110735 | Managing performance policies based on workload scalability | Paul S. Diefenbaugh, Andrew D. Henroid, Eliezer Weissmann | 2015-08-18 |
| 9098261 | User level control of power management policies | Jeremy J. Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh, Eliezer Weissmann +7 more | 2015-08-04 |
| 9092581 | Virtualized communication sockets for multi-flow access to message channel infrastructure within CPU | Daniel Borkowski | 2015-07-28 |
| 9087146 | Wear-out equalization techniques for multiple functional units | Stefan Rusu, Zhiguo Wang | 2015-07-21 |
| 9086834 | Controlling configurable peak performance limits of a processor | Jeremy J. Shrall, Stephen H. Gunther, Ryan D. Wells, Shaun M. Conrad | 2015-07-21 |
| 9075556 | Controlling configurable peak performance limits of a processor | Jeremy J. Shrall, Stephen H. Gunther, Ryan D. Wells, Shaun M. Conrad | 2015-07-07 |
| 9075614 | Managing power consumption in a multi-core processor | Eric Fetzer, Reid James Riedlinger, Don Soltis, William J. Bowhill, Satish Shrimali +5 more | 2015-07-07 |
| 9069555 | Managing power consumption in a multi-core processor | Eric Fetzer, Reid J. Reidlinger, Don Soltis, William J. Bowhill, Satish Shrimali +5 more | 2015-06-30 |
| 9053244 | Utilization-aware low-overhead link-width modulation for power reduction in interconnects | Ankush Varma, Buck Gremel, Robert G. Blankenship, Michael Cole | 2015-06-09 |
| 9037840 | Mechanism to provide workload and configuration-aware deterministic performance for microprocessors | Ankush Varma, Martin T. Rowland, Chris Poirier, Eric J. Dehaemer, Avinash N. Ananthakrishnan +9 more | 2015-05-19 |
| 8966299 | Optimizing power usage by factoring processor architectural events to PMU | Yen-Cheng Liu, P Keong Or, Ganapati Srinivasa | 2015-02-24 |
| 8914650 | Dynamically adjusting power of non-core processor circuitry including buffer circuitry | Dean Mulla, Vivek Garg, Mark Rowland, Suresh Doraiswamy, Ganapati Srinivasa +1 more | 2014-12-16 |
| 8705311 | Forming multiprocessor systems using dual processors | Ganapati Srinivasa | 2014-04-22 |
| 8700933 | Optimizing power usage by factoring processor architectural events to PMU | Yen-Cheng Liu, P Keong Or, Ganapati Srinivasa | 2014-04-15 |
| 8473766 | Optimizing power usage by processor cores based on architectural events | Yen-Cheng Liu, P. Keong Or, Ganapati Srinivasa | 2013-06-25 |
| 8412970 | Optimizing power usage by factoring processor architectural events to PMU | Yen-Cheng Liu, P Keong Or, Ganapati Srinivasa | 2013-04-02 |
| 8407432 | Cache coherency sequencing implementation and adaptive LLC access priority control for CMP | Zhong-Ning Cai, Yen-Cheng Liu, Jeffrey D. Gilbert | 2013-03-26 |
| 8171231 | System and method for aggregating core-cache clusters in order to produce multi-core processors | — | 2012-05-01 |