Issued Patents All Time
Showing 126–150 of 188 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7620876 | Reducing false positives in configuration error detection for programmable devices | Robert Blake, Richard G. Cliff, Srinivas T. Reddy | 2009-11-17 |
| 7589555 | Variable sized soft memory macros in structured cell arrays, and related methods | — | 2009-09-15 |
| 7583103 | Configurable time borrowing flip-flops | David Cashman | 2009-09-01 |
| 7584447 | PLD architecture for flexible placement of IP function blocks | Andy L. Lee, Cameron McClintock, Brian Johnson, Richard G. Cliff, Srinivas T. Reddy +3 more | 2009-09-01 |
| 7580824 | Apparatus and methods for modeling power characteristics of electronic circuitry | Thomas Yau-Tsun Wong | 2009-08-25 |
| 7573317 | Apparatus and methods for adjusting performance of integrated circuits | Vaughn Betz, Irfan Rahim, Peter J. McElheny, Yow-Juang Liu, Bruce B. Pedersen | 2009-08-11 |
| 7558812 | Structures for LUT-based arithmetic in PLDs | Ketan Padalia, David Cashman, Andy L. Lee, Jay Schleicher, Jinyong Yuan +1 more | 2009-07-07 |
| 7538579 | Omnibus logic element | James Schleicher, Richard Yuan, Bruce B. Pedersen, Sinan Kaptanoglu, Gregg William Baeckler +4 more | 2009-05-26 |
| 7508231 | Programmable logic device having redundancy with logic element granularity | David Cashman | 2009-03-24 |
| 7459932 | Programmable logic device having logic modules with improved register capabilities | — | 2008-12-02 |
| 7456653 | Programmable logic device having logic array block interconnect lines that can interconnect logic elements in different logic blocks | David Cashman | 2008-11-25 |
| 7432734 | Versatile logic element and logic array block | Paul Leventis, Andy L. Lee, Henry Kim, Bruce B. Pedersen, Chris Wysocki +4 more | 2008-10-07 |
| 7405589 | Apparatus and methods for power management in integrated circuits | Christopher F. Lane, Sarathy Sribhashyam, Srinivas Perisetty, Tim Vanderhoek, Vaughn Betz +2 more | 2008-07-29 |
| 7400167 | Apparatus and methods for optimizing the performance of programmable logic devices | Vaughn Betz, Paul Leventis, Christopher F. Lane, Andy L. Lee, Jeffrey T. Watt +1 more | 2008-07-15 |
| 7391236 | Distributed memory in field-programmable gate array integrated circuit devices | Paul Leventis, Vaughn Betz, Thomas Yau-Tsun Wong, Andy L. Lee, Philip Pan | 2008-06-24 |
| 7368944 | Organizations of logic modules in programmable logic devices | Michael D. Hutton, Bruce B. Pedersen, Sinan Kaptanoglu, Tim Vanderhoek | 2008-05-06 |
| 7330052 | Area efficient fractureable logic elements | Sinan Kaptanoglu, Bruce B. Pedersen, James Schleicher, Jinyong Yuan, Michael D. Hutton | 2008-02-12 |
| 7328377 | Error correction for programmable logic integrated circuits | Vaughn Betz | 2008-02-05 |
| 7323902 | Fracturable lookup table and logic element | Bruce B. Pedersen, Sinan Kaptanoglu, Andy L. Lee | 2008-01-29 |
| 7312633 | Programmable routing structures providing shorter timing delays for input/output signals | Michael D. Hutton | 2007-12-25 |
| 7312632 | Fracturable lookup table and logic element | Bruce B. Pedersen, Sinan Kaptanoglu, Andy L. Lee | 2007-12-25 |
| 7304499 | Distributed random access memory in a programmable logic device | Paul Leventis, Vaughn Betz | 2007-12-04 |
| 7283942 | High speed techniques for simulating circuits | — | 2007-10-16 |
| 7268584 | Adder circuitry for a programmable logic device | David Cashman, Gregg William Baeckler, Ketan Padalia | 2007-09-11 |
| 7253660 | Multiplexing device including a hardwired multiplexer in a programmable logic device | Paul Leventis, Bruce B. Pedersen, Chris Lane, Srinivas T. Reddy | 2007-08-07 |