Issued Patents All Time
Showing 51–69 of 69 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10777656 | Fin cut and fin trim isolation for advanced integrated circuit structure fabrication | Tahir Ghani, Byron Ho, Curtis W. Ward, Michael L. Hattendorf | 2020-09-15 |
| 10756204 | Fin trim isolation with single gate spacing for advanced integrated circuit structure fabrication | Tahir Ghani, Byron Ho, Michael L. Hattendorf | 2020-08-25 |
| 10741669 | Differentiated voltage threshold metal gate structures for advanced integrated circuit structure fabrication | Jeffrey S. Leib, Jenny Hu, Anindya Dasgupta, Michael L. Hattendorf | 2020-08-11 |
| 10734379 | Fin end plug structures for advanced integrated circuit structure fabrication | Byron Ho, Chun-Kuo HUANG, Erica J. Thompson, Jeanne Luce, Michael L. Hattendorf +1 more | 2020-08-04 |
| 10727313 | Dual metal gate structures for advanced integrated circuit structure fabrication | Jeffrey S. Leib, Jenny Hu, Anindya Dasgupta, Michael L. Hattendorf | 2020-07-28 |
| 10707133 | Trench plug hardmask for advanced integrated circuit structure fabrication | Anthony St. Amour, Michael L. Hattendorf | 2020-07-07 |
| 10677543 | Cooling tower | Yohann Lilian Rousselet, Dina Malamud, Kevin Egolf, Lukasz Sztobryn | 2020-06-09 |
| 10615265 | Gate cut and fin trim isolation for advanced integrated circuit structure fabrication | Tahir Ghani, Byron Ho, Michael L. Hattendorf | 2020-04-07 |
| 10553430 | Technologies for inverting lithographic patterns and semiconductor devices including high aspect ratio structures | Anthony St. Amour | 2020-02-04 |
| 10541316 | Contact over active gate structures for advanced integrated circuit structure fabrication | Andrew W. Yeoh, Tahir Ghani, Atul MADHAVAN, Michael L. Hattendorf | 2020-01-21 |
| 10460993 | Fin cut and fin trim isolation for advanced integrated circuit structure fabrication | Tahir Ghani, Byron Ho, Curtis W. Ward, Michael L. Hattendorf | 2019-10-29 |
| 10410867 | Confined and scalable helmet | Vyom Sharma, Rohan K. Bambery, Szuya S. Liao, Gaurav Thareja | 2019-09-10 |
| 10304940 | Gate cut and fin trim isolation for advanced integrated circuit structure fabrication | Tahir Ghani, Byron Ho, Michael L. Hattendorf | 2019-05-28 |
| 10121882 | Gate line plug structures for advanced integrated circuit structure fabrication | Byron Ho, Michael L. Hattendorf | 2018-11-06 |
| 10121875 | Replacement gate structures for advanced integrated circuit structure fabrication | Byron Ho, Steven Jaloviar, Jeffrey S. Leib, Michael L. Hattendorf | 2018-11-06 |
| 7861406 | Method of forming CMOS transistors with dual-metal silicide formed through the contact openings | Saurabh Lodha, Pushkar Ranade | 2011-01-04 |
| 7691752 | Methods of forming improved EPI fill on narrow isolation bounded source/drain regions and structures formed thereby | Pushkar Ranade, Keith E. Zawadzki | 2010-04-06 |
| 7338847 | Methods of manufacturing a stressed MOS transistor structure | M. Shaheed, Thomas Hoffmann, Mark Armstrong | 2008-03-04 |
| 6870179 | Increasing stress-enhanced drive current in a MOS transistor | M. Shaheed, Thomas Hoffmann, Mark Armstrong | 2005-03-22 |