Issued Patents All Time
Showing 51–75 of 87 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9293579 | Method of forming stacked trench contacts and structures formed thereby | Oleg Golonzka | 2016-03-22 |
| 9252267 | Method of forming stacked trench contacts and structures formed thereby | Oleg Golonzka | 2016-02-02 |
| 9224602 | Sub-second annealing lithography techniques | Aravind S. Killampalli, Charles H. Wallace | 2015-12-29 |
| 8941214 | Semiconductor device having a necked semiconductor body and method of forming semiconductor bodies of varying width | — | 2015-01-27 |
| 8803245 | Method of forming stacked trench contacts and structures formed thereby | Oleg Golonzka | 2014-08-12 |
| 8154087 | Multi-component strain-inducing semiconductor regions | Ted COOK, JR., Anand S. Murthy | 2012-04-10 |
| 7943469 | Multi-component strain-inducing semiconductor regions | Ted COOK, JR., Anand S. Murthy | 2011-05-17 |
| 7943992 | Metal gate structures with recessed channel | Rishabh Mehandru | 2011-05-17 |
| 7829943 | Low-k isolation spacers for conductive regions | — | 2010-11-09 |
| 7768074 | Dual salicide integration for salicide through trench contacts and structures formed thereby | Oleg Golonzka | 2010-08-03 |
| 7732285 | Semiconductor device having self-aligned epitaxial source and drain extensions | Tahir Ghani, Anand S. Murthy, Harry Gomez | 2010-06-08 |
| 7687364 | Low-k isolation spacers for conductive regions | — | 2010-03-30 |
| 7663192 | CMOS device and method of manufacturing same | Anand S. Murthy, Mark Liu, Daniel B. Aubertine | 2010-02-16 |
| 7335959 | Device with stepped source/drain region profile | Giuseppe Curello, Sunit Tyagi, Chris Auth | 2008-02-26 |
| 7199414 | Stress-reduced layer system for use in storage capacitors | Matthias Goldbach, Annette Sanger | 2007-04-03 |
| 7129173 | Process for producing and removing a mask layer | Heike Drummer, Franz Kreupl, Annette Sanger, Manfred Engelhardt, Peter Thieme | 2006-10-31 |
| 7112859 | Stepped tip junction with spacer layer | Ibrahim Ban, Sanjay Natarajan, Mark Bohr | 2006-09-26 |
| 7041568 | Method for the production of a self-adjusted structure on a semiconductor wafer | Matthias Goldbach, Thomas Hecht, Jorn Lutzen | 2006-05-09 |
| 7009900 | Circuit arrangement for reading out, evaluating and reading in again a charge state into a memory cell | Matthias Goldbach | 2006-03-07 |
| 6998307 | Method for fabricating a storage capacitor | Annette Sanger, Dirk Schumann | 2006-02-14 |
| 6987295 | Trench capacitor and method for fabricating the trench capacitor | Annette Sanger, Dirk Schumann | 2006-01-17 |
| 6960524 | Method for production of a metallic or metal-containing layer | Thomas Hecht, Annette Saenger | 2005-11-01 |
| 6916704 | Multiple deposition of metal layers for the fabrication of an upper capacitor electrode of a trench capacitor | Martin Gutsche, Annette Sanger, Harald Seidl | 2005-07-12 |
| 6835417 | Method and device for depositing thin layers via ALD/CVD processes in combination with rapid thermal processes | Annette Saenger, Harald Seidl, Thomas Hecht, Martin Gutsche | 2004-12-28 |
| 6806037 | Method for producing and/or renewing an etching mask | Matthias Goldbach, Thomas Hecht | 2004-10-19 |