Issued Patents All Time
Showing 51–75 of 85 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8592911 | Asymmetric semiconductor device having a high-k/metal gate and method of manufacturing the same | Qingqing Liang, Huilong Zhu | 2013-11-26 |
| 8557677 | Stack-type semiconductor device and method for manufacturing the same | Qingqing Liang, Chao Zhao, Huilong Zhu | 2013-10-15 |
| 8536053 | Method for restricting lateral encroachment of metal silicide into channel region | Jun Luo, Chao Zhao | 2013-09-17 |
| 8525188 | Shallow trench isolation structure and method for forming the same | Qingqing Liang, Haizhou Yin | 2013-09-03 |
| 8513780 | Semiconductor device having inter-level dielectric layer with hole-sealing and method for manufacturing the same | Qingqing Liang | 2013-08-20 |
| 8513742 | Method for manufacturing contact and semiconductor device having said contact | Qingqing Liang | 2013-08-20 |
| 8492210 | Transistor, semiconductor device comprising the transistor and method for manufacturing the same | Qingqing Liang, Huilong Zhu | 2013-07-23 |
| 8492206 | Semiconductor device structure and method for manufacturing the same | Jun Luo, Qingqing Liang, Huilong Zhu | 2013-07-23 |
| 8481379 | Method for manufacturing fin field-effect transistor | Qingqing Liang, Huilong Zhu | 2013-07-09 |
| 8460988 | Method for manufacturing semiconductor device | Qingqing Liang | 2013-06-11 |
| 8455323 | Method for manufacturing semiconductor wafer | Qingqing Liang, Chao Zhao | 2013-06-04 |
| 8420492 | MOS transistor and method for forming the same | Qingqing Liang, Da Yang, Chao Zhao | 2013-04-16 |
| 8410609 | Semiconductor device having carbon nanotube interconnects contact deposited with different orientation and method for manufacturing the same | Qingqing Liang, Zhijiong Luo, Huilong Zhu | 2013-04-02 |
| 8278721 | Contact hole, semiconductor device and method for forming the same | Qingqing Liang | 2012-10-02 |
| 8269307 | Shallow trench isolation structure and method for forming the same | Haizhou Yin, Qingqing Liang, Huilong Zhu | 2012-09-18 |
| 8008213 | Self-assembly process for memory array | Li Xiao, Jingyan Zhang | 2011-08-30 |
| 7767508 | Method for forming offset spacers for semiconductor device arrangements | Philip A. Fisher, Laura A. Brown, Johannes Groschopf | 2010-08-03 |
| 7745296 | Raised source and drain process with disposable spacers | Johannes M. van Meer | 2010-06-29 |
| 7569892 | Method and structure for forming self-aligned, dual stress liner for CMOS devices | Huilong Zhu, Effendi Leobandung | 2009-08-04 |
| 7485521 | Self-aligned dual stressed layers for NFET and PFET | Huilong Zhu, Brian L. Tessier | 2009-02-03 |
| 7456058 | Stressed MOS device and methods for its fabrication | Igor Peidous, Linda Black | 2008-11-25 |
| 7288451 | Method and structure for forming self-aligned, dual stress liner for CMOS devices | Huilong Zhu, Effendi Leobandung | 2007-10-30 |
| 7244644 | Undercut and residual spacer prevention for dual stressed layers | Huilong Zhu, Brian L. Tessier, Ying Li | 2007-07-17 |
| 7176531 | CMOS gates formed by integrating metals having different work functions and having a high-k gate dielectric | Qi Xiang, Jung-Suk Goo, Allison Holbrook, Joong S. Jeon, George Jonathan Kluth | 2007-02-13 |
| 7169676 | Semiconductor devices and methods for forming the same including contacting gate to source | — | 2007-01-30 |