Issued Patents All Time
Showing 76–100 of 108 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7687343 | Storage capacitor, a memory device and a method of manufacturing the same | Peter Moll, Peter Baars, Till Schloesser, Klaus Muemmler | 2010-03-30 |
| 7642586 | Integrated memory cell array | — | 2010-01-05 |
| 7642572 | Integrated circuit having a memory cell array and method of forming an integrated circuit | Martin Popp, Till Schloesser, Ulrike Gruening-von Schwerin | 2010-01-05 |
| 7635893 | Transistor, memory cell array and method of manufacturing a transistor | Till Schloesser, Ulrike Gruening von Schwerin | 2009-12-22 |
| 7605037 | Manufacturing method for an integrated semiconductor memory device and corresponding semiconductor memory device | — | 2009-10-20 |
| 7605032 | Method for producing a trench transistor and trench transistor | Richard Luyken, Hans-Peter Moll, Martin Popp, Till Schloesser, Marc Strasser | 2009-10-20 |
| 7569878 | Fabricating a memory cell array | Ulrike Gruening von Schwerin | 2009-08-04 |
| 7442609 | Method of manufacturing a transistor and a method of forming a memory device with isolation trenches | Peng Wang, Joachim Nuetzel, Till Schloesser, Marc Strasser, Richard Luyken | 2008-10-28 |
| 7301192 | Dram cell pair and dram memory cell array | Johann Harter, Wolfgang Mueller, Wolfgang Bergner, Ulrike Grüning Von Schwerin, Till Schloesser | 2007-11-27 |
| 7271058 | Storage capacitor and method of manufacturing a storage capacitor | — | 2007-09-18 |
| 7244980 | Line mask defined active areas for 8F2 DRAM cells with folded bit lines and deep trench patterns | Ramachandra Divakaruni, Larry Nesbit | 2007-07-17 |
| 7208373 | Method of forming a memory cell array and a memory cell array | — | 2007-04-24 |
| 7141845 | DRAM cell array and memory cell arrangement having vertical memory cells and methods for fabricating the same | Dirk Manger, Till Schloesser, Bernd Goebel, Wolfgang Mueller | 2006-11-28 |
| 7132333 | Transistor, memory cell array and method of manufacturing a transistor | Till Schloesser, Ulrike Gruening-von Schwerin | 2006-11-07 |
| 7078290 | Method for forming a top oxide with nitride liner | — | 2006-07-18 |
| 7067372 | Method for fabricating a memory cell having a trench | Martin Schrems | 2006-06-27 |
| 6946345 | Self-aligned buried strap process using doped HDP oxide | Jochen Beintner, Wolfgang Bergner, Richard A. Conti, Andreas Knorr | 2005-09-20 |
| 6893938 | STI formation for vertical and planar transistors | Munir D. Naeem, Hiroyuki Akatsu, Byeong Y. Kim, David Mark Dobuzinksy, Johnathan E. Faltermeier | 2005-05-17 |
| 6825096 | Method of forming an alignment mark structure using standard process steps for forming vertical gate transistors | — | 2004-11-30 |
| 6806200 | Method of improving etch uniformity in deep silicon etching | David M. Dobuzinsky, Siddhartha Panda, Richard S. Wise | 2004-10-19 |
| 6797636 | Process of fabricating DRAM cells with collar isolation layers | Helmut Tews | 2004-09-28 |
| 6762443 | Vertical transistor and transistor fabrication method | — | 2004-07-13 |
| 6713884 | Method of forming an alignment mark structure using standard process steps for forming vertical gate transistors | — | 2004-03-30 |
| 6667504 | Self-aligned buried strap process using doped HDP oxide | Jochen Beintner, Wolfgang Bergner, Richard A. Conti, Andreas Knorr | 2003-12-23 |
| 6610573 | Method for forming a single wiring level for transistors with planar and vertical gates on the same substrate | — | 2003-08-26 |