Issued Patents All Time
Showing 101–125 of 414 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10346134 | Perform sign operation decimal instruction | Jonathan D. Bradbury, Reid T. Copeland, Silvia M. Mueller | 2019-07-09 |
| 10348506 | Determination of state of padding operation | Dan F. Greiner, Christian Zoellin | 2019-07-09 |
| 10346305 | Interprocessor memory status communication | Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum | 2019-07-09 |
| 10324728 | Lightweight interrupts for condition checking | Giles R. Frazier, Michael K. Gschwind, Christian Jacobi, Chung-Lung K. Shum, Joran S. C. Siu +1 more | 2019-06-18 |
| 10303569 | Simplified processor sparing | Gregory W. Alexander, Brian D. Barrick, Shimon Ben-Yehuda, Ophir Erez, Anthony Saporito | 2019-05-28 |
| 10303478 | Convert from zoned format to decimal floating point format | Steven R. Carlough, Reid T. Copeland, Charles W. Gainey, Jr., Marcel Mitran, Eric M. Schwarz | 2019-05-28 |
| 10296344 | Convert from zoned format to decimal floating point format | Steven R. Carlough, Reid T. Copeland, Charles W. Gainey, Jr., Marcel Mitran, Eric M. Schwarz | 2019-05-21 |
| 10282327 | Test pending external interruption instruction | Mark S. Farrell, Dan F. Greiner, Jeffrey P. Kubala, James H. Mulder | 2019-05-07 |
| 10275254 | Spin loop delay instruction | Fadi Y. Busaba, Christian Jacobi, Anthony Saporito, Eric M. Schwarz | 2019-04-30 |
| 10261828 | Interprocessor memory status communication | Michael K. Gschwind | 2019-04-16 |
| 10261827 | Interprocessor memory status communication | Michael K. Gschwind | 2019-04-16 |
| 10235201 | Dynamic releasing of cache lines | Jonathan D. Bradbury, Michael K. Gschwind, Chung-Lung K. Shum | 2019-03-19 |
| 10235174 | Conditional instruction end operation | Dan F. Greiner, Christian Jacobi, Marcel Mitran, Donald W. Schmidt | 2019-03-19 |
| 10235138 | Instruction to provide true random numbers | Dan F. Greiner, Bernd Nerz, Tamas Visegrady, Christian Zoellin | 2019-03-19 |
| 10228943 | Prefetching of discontiguous storage locations in anticipation of transactional execution | Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael, Valentina Salapura +1 more | 2019-03-12 |
| 10223214 | Randomized testing within transactional execution | Dan F. Greiner, Christian Jacobi | 2019-03-05 |
| 10223154 | Hint instruction for managing transactional aborts in transactional memory computing environments | Fadi Y. Busaba, Harold W. Cain, III, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael +2 more | 2019-03-05 |
| 10216480 | Shift and divide operations using floating-point arithmetic | Eric M. Schwarz, Craig Slegel | 2019-02-26 |
| 10210019 | Hint instruction for managing transactional aborts in transactional memory computing environments | Fadi Y. Busaba, Harold W. Cain, III, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael +2 more | 2019-02-19 |
| 10185588 | Transaction begin/end instructions | Dan F. Greiner, Christian Jacobi, Marcel Mitran | 2019-01-22 |
| 10175946 | Perform sign operation decimal instruction | Jonathan D. Bradbury, Reid T. Copeland, Silvia M. Mueller | 2019-01-08 |
| 10168961 | Hardware transaction transient conflict resolution | Jonathan D. Bradbury, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz +1 more | 2019-01-01 |
| 10169239 | Managing a prefetch queue based on priority indications of prefetch requests | Dan F. Greiner, Michael K. Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum | 2019-01-01 |
| 10169038 | Compare and delay instructions | Charles W. Gainey, Jr., Dan F. Greiner, Christian Jacobi, Marcel Mitran, Donald W. Schmidt | 2019-01-01 |
| 10162743 | Prefetch insensitive transactional memory | Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum | 2018-12-25 |