Issued Patents All Time
Showing 151–175 of 414 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9952804 | Hardware transaction transient conflict resolution | Jonathan D. Bradbury, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz +1 more | 2018-04-24 |
| 9946542 | Instruction to load data up to a specified memory boundary indicated by the instruction | Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Eric M. Schwarz | 2018-04-17 |
| 9946494 | Hardware transaction transient conflict resolution | Jonathan D. Bradbury, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz +1 more | 2018-04-17 |
| 9940135 | Instruction stream modification for memory transaction protection | Fadi Y. Busaba, Michael K. Gschwind, Maged M. Michael, Chung-Lung K. Shum, Valentina Salapura | 2018-04-10 |
| 9934159 | Dynamic address translation with fetch protection in an emulated environment | Dan F. Greiner, Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer +1 more | 2018-04-03 |
| 9928173 | Conditional inclusion of data in a transactional memory read set | Michael K. Gschwind, Eric M. Schwarz, Chung-Lung K. Shum | 2018-03-27 |
| 9928064 | Instruction stream modification for memory transaction protection | Fadi Y. Busaba, Michael K. Gschwind, Maged M. Michael, Chung-Lung K. Shum, Valentina Salapura | 2018-03-27 |
| 9921895 | Transactional memory operations with read-only atomicity | Michael K. Gschwind, Eric M. Schwarz, Chung-Lung K. Shum | 2018-03-20 |
| 9921872 | Interprocessor memory status communication | Dan F. Greiner, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum | 2018-03-20 |
| 9921849 | Address expansion and contraction in a multithreading computer system | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +4 more | 2018-03-20 |
| 9921848 | Address expansion and contraction in a multithreading computer system | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +4 more | 2018-03-20 |
| 9921834 | Prefetching of discontiguous storage locations in anticipation of transactional execution | Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael, Valentina Salapura +1 more | 2018-03-20 |
| 9916180 | Interprocessor memory status communication | Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum | 2018-03-13 |
| 9916179 | Interprocessor memory status communication | Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum | 2018-03-13 |
| 9910769 | Alignment based block concurrency for accessing memory | Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi | 2018-03-06 |
| 9904618 | Alignment based block concurrency for accessing memory | Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi | 2018-02-27 |
| 9898331 | Dynamic releasing of cache lines | Jonathan D. Bradbury, Michael K. Gschwind, Chung-Lung K. Shum | 2018-02-20 |
| 9898294 | Selectively blocking branch prediction for a predetermined number of instructions | James J. Bonanno, Ulrich Mayer, Anthony Saporito, Chung-Lung K. Shum | 2018-02-20 |
| 9898290 | Efficiency for coordinated start interpretive execution exit for a multithreaded processor | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +4 more | 2018-02-20 |
| 9898289 | Coordinated start interpretive execution exit for a multithreaded processor | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +4 more | 2018-02-20 |
| 9891922 | Selectively blocking branch prediction for a predetermined number of instructions | James J. Bonanno, Ulrich Mayer, Anthony Saporito, Chung-Lung K. Shum | 2018-02-13 |
| 9864692 | Managing read tags in a transactional memory | Dan F. Greiner, Michael K. Gschwind, Eric M. Schwarz, Chung-Lung K. Shum | 2018-01-09 |
| 9864690 | Detecting cache conflicts by utilizing logical address comparisons in a transactional memory | Michael K. Gschwind, Eric M. Schwarz, Chung-Lung K. Shum | 2018-01-09 |
| 9858082 | Restricted instructions in transactional execution | Dan F. Greiner, Christian Jacobi | 2018-01-02 |
| 9851969 | Function virtualization facility for function query of a processor | Dan F. Greiner, Damian L. Osisek | 2017-12-26 |