Issued Patents All Time
Showing 51–75 of 123 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7503020 | IC layout optimization to improve yield | Faye D. Baker, Albert M. Chu, Michael S. Gray, Jason D. Hibbeler, Daniel N. Maynard +2 more | 2009-03-10 |
| 7484197 | Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designs | Michael S. Gray, Fook-Luen Heng, Jason D. Hibbeler, Kevin W. McCullen, Rani Narayan +2 more | 2009-01-27 |
| 7433302 | Ethernet network implementing redundancy using a single category 5 cable | — | 2008-10-07 |
| 7419546 | Gas diffusion electrodes, membrane-electrode assemblies and method for the production thereof | Andrea F. Gulla, Emory S. De Castro, Enrico Ramunni | 2008-09-02 |
| 7404159 | Critical area computation of composite fault mechanisms using Voronoi diagrams | Evanthia Papadopoulou, Mervyn Y. Tan | 2008-07-22 |
| 7398635 | Method and device for aligning a receiving envelope in a mail inserter | James A. Fairweather, George J. Doutney, Thomas M. Lyga, Daniel P. Goslicki, Jr. | 2008-07-15 |
| 7389480 | Content based yield prediction of VLSI designs | Daria R. Dooling, Jason D. Hibbeler, Daniel N. Maynard, Sarah C. Prue, Ralph J. Williams | 2008-06-17 |
| 7310788 | Sample probability of fault function determination using critical defect size map | Mervyn Y. Tan | 2007-12-18 |
| 7302653 | Probability of fault function determination using critical defect size map | Mervyn Y. Tan | 2007-11-27 |
| 7302651 | Technology migration for integrated circuits with radical design restrictions | Cam V. Endicott, Fook-Luen Heng, Jason D. Hibbeler, Kevin W. McCullen, Rani Narayan +2 more | 2007-11-27 |
| 7289659 | Method and apparatus for manufacturing diamond shaped chips | John M. Cohn, Scott Whitney Gould, Peter A. Habitz, Juergen Koehl, Gustavo E. Tellez +2 more | 2007-10-30 |
| 7260790 | Integrated circuit yield enhancement using Voronoi diagrams | Michael S. Gray, Jason D. Hibbeler, Mervyn Y. Tan, Robert F. Walker | 2007-08-21 |
| 7257783 | Technology migration for integrated circuits with radical design restrictions | Cam V. Endicott, Fook-Luen Heng, Jason D. Hibbeler, Kevin W. McCullen, Rani Narayan +2 more | 2007-08-14 |
| 7240306 | Integrated circuit layout critical area determination using Voronoi diagrams and shape biasing | Peter Chan, Evanthia Papadopoulou, Sarah C. Prue, Mervyn Y. Tan | 2007-07-03 |
| 7143371 | Critical area computation of composite fault mechanisms using voronoi diagrams | Evanthia Papadopoulou, Mervyn Y. Tan | 2006-11-28 |
| 7124387 | Integrated circuit macro placing system and method | Steven G. Lovejoy, Kevin W. McCullen | 2006-10-17 |
| 7089511 | Framework for hierarchical VLSI design | Ulrich A. Finkler, Mark A. Lavin, Robert T. Sayah | 2006-08-08 |
| 6988255 | Generation of refined switching windows in static timing analysis | Ravishankar Arunachalam, David J. Hathaway | 2006-01-17 |
| 6986109 | Practical method for hierarchical-preserving layout optimization of integrated circuit layout | Fook-Luen Heng, Alexey Y. Lvov, Kevin W. McCullen, Sriram Peri, Gustavo E. Tellez | 2006-01-10 |
| 6967185 | Synthesis of noble metal, sulphide catalysts in a sulfide ion-free aqueous environment | Andrea F. Gulla | 2005-11-22 |
| 6948146 | Simplified tiling pattern method | John M. Cohn, Peter A. Habitz, William C. Leipold, Ivan L. Wemple, Paul S. Zuchowski | 2005-09-20 |
| 6941528 | Use of a layout-optimization tool to increase the yield and reliability of VLSI designs | Jason D. Hibbeler, Gustavo E. Tellez | 2005-09-06 |
| 6904575 | Method for improving chip yields in the presence of via flaring | Gustavo E. Tellez | 2005-06-07 |
| 6855660 | Rhodium electrocatalyst and method of preparation | Yu-Min Tsou, Hua Deng, Gian Nicola Martelli, Emory S. De Castro | 2005-02-15 |
| 6790303 | Apparatus and method for sealing an envelope | Carl R. Chapman, David K. Halden, Thomas M. Lyga, Michael Roche | 2004-09-14 |