Issued Patents All Time
Showing 126–150 of 508 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7822889 | Direct/indirect transmission of information using a multi-tiered full-graph interconnect architecture | Lakshminarayana B. Arimilli, Ramakrishnan Rajamony | 2010-10-26 |
| 7818388 | Data processing system, method and interconnect fabric supporting multiple planes of processing nodes | Benjiman L. Goodman, Guy L. Guthrie, Praveen S. Reddy, William J. Starke | 2010-10-19 |
| 7818364 | Method and data processing system for microprocessor communication in a cluster-based multi-processor system | Robert Alan Cargnoni, Derek E. Williams, Kenneth L. Wright | 2010-10-19 |
| 7809970 | System and method for providing a high-speed message passing interface for barrier operations in a multi-tiered full-graph interconnect architecture | Lakshminarayana B. Arimilli, Ramakrishnan Rajamony | 2010-10-05 |
| 7793158 | Providing reliability of communication between supernodes of a multi-tiered full-graph interconnect architecture | Lakshminarayana B. Arimilli, Ramakrishnan Rajamony | 2010-09-07 |
| 7783842 | Cache coherent I/O communication | Robert Alan Cargnoni, Guy L. Guthrie, William J. Starke | 2010-08-24 |
| 7779148 | Dynamic routing based on information of not responded active source requests quantity received in broadcast heartbeat signal and stored in local data structure for other processor chips | Lakshminarayana B. Arimilli, Bernard C. Drerup, Jody B. Joyner, Jerry Don Lewis | 2010-08-17 |
| 7770077 | Using cache that is embedded in a memory hub to replace failed memory cells in a memory subsystem | Kevin C. Gower, Warren E. Maule | 2010-08-03 |
| 7769892 | System and method for handling indirect routing of information between supernodes of a multi-tiered full-graph interconnect architecture | Lakshminarayana B. Arimilli, Ramakrishnan Rajamony | 2010-08-03 |
| 7769891 | System and method for providing multiple redundant direct routes between supernodes of a multi-tiered full-graph interconnect architecture | Lakshminarayana B. Arimilli, Ramakrishnan Rajamony | 2010-08-03 |
| 7734877 | Method and data processing system for processor-to-processor communication in a clustered multi-processor system | Robert Alan Cargnoni, Derek E. Williams, Kenneth L. Wright | 2010-06-08 |
| 7698373 | Method, processing unit and data processing system for microprocessor communication in a multi-processor system | Robert Alan Cargnoni, Derek E. Williams, Kenneth L. Wright | 2010-04-13 |
| 7617378 | Multiprocessor system with retry-less TLBI protocol | Guy L. Guthrie, Kirk Samuel Livingston | 2009-11-10 |
| 7610458 | Data processing system, processor and method of data processing that support memory access according to diverse memory models | Thomas M. Capasso, Guy L. Guthrie, Hugh Shen, William J. Starke | 2009-10-27 |
| 7586936 | Host Ethernet adapter for networking offload in server environment | Claude Basso, Jean Calvignac, Chih-jen Chang, Philippe Damon, Ronald Edward Fuhs +5 more | 2009-09-08 |
| 7526631 | Data processing system with backplane and processor books configurable to support both technical and commercial workloads | Vicente Enrique Chung, Jody B. Joyner, Jerry Don Lewis | 2009-04-28 |
| 7523260 | Propagating data using mirrored lock caches | Rama K. Govindaraju, Peter Hochschild, Bruce Mealey, Satya P. Sharma, Balaram Sinharoy | 2009-04-21 |
| 7506132 | Validity of address ranges used in semi-synchronous memory copy operations | Rama K. Govindaraju, Peter Hochschild, Bruce Mealey, Satya P. Sharma, Balaram Sinharoy | 2009-03-17 |
| 7502917 | High speed memory cloning facility via a lockless multiprocessor mechanism | Benjiman L. Goodman, Jody B. Joyner | 2009-03-10 |
| 7493478 | Enhanced processor virtualization mechanism via saving and restoring soft processor/system states | Robert Alan Cargnoni, Guy L. Guthrie, William J. Starke | 2009-02-17 |
| 7493446 | System and method for completing full updates to entire cache lines stores with address-only bus operations | Guy L. Guthrie, Hugh Shen, Derek E. Williams | 2009-02-17 |
| 7493417 | Method and data processing system for microprocessor communication using a processor interconnect in a multi-processor system | Robert Alan Cargnoni, Derek E. Williams, Kenneth L. Wright | 2009-02-17 |
| 7484062 | Cache injection semi-synchronous memory copy operation | Rama K. Govindaraju, Peter Hochschild, Bruce Mealey, Satya P. Sharma, Balaram Sinharoy | 2009-01-27 |
| 7475399 | Method and data processing system optimizing performance through reporting of thread-level hardware resource utilization | Randal C. Swanberg | 2009-01-06 |
| 7475196 | Processor, data processing system, and method for initializing a memory block in a data processing system having multiple coherency domains | Guy L. Guthrie, William J. Starke, Derek E. Williams | 2009-01-06 |