Issued Patents All Time
Showing 101–125 of 508 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8015379 | Wake-and-go mechanism with exclusive system bus response | Satya P. Sharma, Randal C. Swanberg | 2011-09-06 |
| 8014387 | Providing a fully non-blocking switch in a supernode of a multi-tiered full-graph interconnect architecture | Lakshminarayana B. Arimilli, Ramakrishnan Rajamony | 2011-09-06 |
| 7996564 | Remote asynchronous data mover | Lakshminarayana B. Arimilli, Ronald Nick Kalla, Ramakrishnan Rajamony, Balaram Sinharoy, William E. Speight +1 more | 2011-08-09 |
| 7991981 | Completion of asynchronous memory move in the presence of a barrier operation | Robert S. Blackmore, Chulho Kim, Balaram Sinharoy, Hanhong Xue | 2011-08-02 |
| 7966454 | Issuing global shared memory operations via direct cache injection to a host fabric interface | Lakshimarayana B. Arimilli, Robert S. Blackmore, Chulho Kim, Ramakrishnan Rajamony, William J. Starke +1 more | 2011-06-21 |
| 7958327 | Performing an asynchronous memory move (AMM) via execution of AMM store instruction within the instruction set architecture | Robert S. Blackmore, Chulho Kim, Balaram Sinharoy, Hanhong Xue | 2011-06-07 |
| 7958309 | Dynamic selection of a memory access size | Lakshminarayana B. Arimilli, Jerry Don Lewis, Warren E. Maule | 2011-06-07 |
| 7958183 | Performing collective operations using software setup and partial software execution at leaf nodes in a multi-tiered full-graph interconnect architecture | Lakshminarayana B. Arimilli, Ramakrishnan Rajamony, William E. Speight | 2011-06-07 |
| 7958182 | Providing full hardware support of collective operations in a multi-tiered full-graph interconnect architecture | Lakshminarayana B. Arimilli, Ramakrishnan Rajamony, William E. Speight | 2011-06-07 |
| 7941627 | Specialized memory move barrier operations | Robert S. Blackmore, Chulho Kim, Balaram Sinharoy, Hanhong Xue | 2011-05-10 |
| 7937570 | Termination of in-flight asynchronous memory move | Robert S. Blackmore, Ronald Nick Kalla, Chulho Kim, Balaram Sinharoy, Hanhong Xue | 2011-05-03 |
| 7930504 | Handling of address conflicts during asynchronous memory move operations | Robert S. Blackmore, Chulho Kim, Balaram Sinharoy, Hanhong Xue | 2011-04-19 |
| 7925842 | Allocating a global shared memory | Robert S. Blackmore, Ramakrishnan Rajamony, William J. Starke | 2011-04-12 |
| 7921316 | Cluster-wide system clock in a multi-tiered full-graph interconnect architecture | Lakshminarayana B. Arimilli, Bernard C. Drerup, Jody B. Joyner, Jerry Don Lewis | 2011-04-05 |
| 7921275 | Method for enabling direct prefetching of data during asychronous memory move operation | Robert S. Blackmore, Chulho Kim, Balaram Sinharoy, Hanhong Xue | 2011-04-05 |
| 7904693 | Full virtualization of resources across an IP interconnect using page frame table | Claude Basso, Jean Calvignac, Piyush Chaudhary, Edward J. Seminaro | 2011-03-08 |
| 7904590 | Routing information through a data processing system implementing a multi-tiered full-graph interconnect architecture | Lakshminarayana B. Arimilli, Ramakrishnan Rajamony, William E. Speight | 2011-03-08 |
| 7900016 | Full virtualization of resources across an IP interconnect | Claude Basso, Jean Calvignac, Piyush Chaudhary, Edward J. Seminaro | 2011-03-01 |
| 7895374 | Dynamic segment sparing and repair in a memory system | Frank D. Ferraiolo, Daniel M. Dreps, Kevin C. Gower, Robert J. Reese | 2011-02-22 |
| 7890703 | Cache injection using semi-synchronous memory copy operation | Rama K. Govindaraju, Peter Hochschild, Bruce Mealey, Satya P. Sharma, Balaram Sinharoy | 2011-02-15 |
| 7882321 | Validity of address ranges used in semi-synchronous memory copy operations | Rama K. Govindaraju, Peter Hochschild, Bruce Mealey, Satya P. Sharma, Balaram Sinharoy | 2011-02-01 |
| 7849298 | Enhanced processor virtualization mechanism via saving and restoring soft processor/system states | Robert Alan Cargnoni, Guy L. Guthrie, William J. Starke | 2010-12-07 |
| 7844746 | Accessing an effective address and determining whether the effective address is associated with remotely coupled I/O adapters | Claude Basso, Jean Calvignac, Edward J. Seminaro | 2010-11-30 |
| 7840703 | System and method for dynamically supporting indirect routing within a multi-tiered full-graph interconnect architecture | Lakshminarayana B. Arimilli, Ramakrishnan Rajamony | 2010-11-23 |
| 7827428 | System for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architecture | Lakshminarayana B. Arimilli, Bernard C. Drerup, Jody B. Joyner, Jerry Don Lewis | 2010-11-02 |