Issued Patents All Time
Showing 76–100 of 508 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8161265 | Techniques for multi-level indirect data prefetching | Balaram Sinharoy, William E. Speight, Lixin Zhang | 2012-04-17 |
| 8161264 | Techniques for data prefetching using indirect addressing with offset | Balaram Sinharoy, William E. Speight, Lixin Zhang | 2012-04-17 |
| 8161263 | Techniques for indirect data prefetching | Balaram Sinharoy, William E. Speight, Lixin Zhang | 2012-04-17 |
| 8145849 | Wake-and-go mechanism with system bus response | Satya P. Sharma, Randal C. Swanberg | 2012-03-27 |
| 8145723 | Complex remote update programming idiom accelerator | Satya P. Sharma, Randal C. Swanberg | 2012-03-27 |
| 8140801 | Efficient and flexible memory copy operation | Rama K. Govindaraju, Peter Hochschild, Bruce Mealey, Satya P. Sharma, Balaram Sinharoy | 2012-03-20 |
| 8140771 | Partial cache line storage-modifying operation based upon a hint | Guy L. Guthrie, William J. Starke, Derek E. Williams | 2012-03-20 |
| 8140731 | System for data processing using a multi-tiered full-graph interconnect architecture | Lakshminarayana B. Arimilli, Ramakrishnan Rajamony, Edward J. Seminaro, William E. Speight | 2012-03-20 |
| 8131935 | Virtual barrier synchronization cache | Guy L. Guthrie, Robert Alan Cargnoni, William J. Starke, Derek E. Williams | 2012-03-06 |
| 8127300 | Hardware based dynamic load balancing of message passing interface tasks | Lakshminarayana B. Arimilli, Ramakrishnan Rajamony, William E. Speight | 2012-02-28 |
| 8127080 | Wake-and-go mechanism with system address bus transaction master | Satya P. Sharma, Randal C. Swanberg | 2012-02-28 |
| 8122132 | Techniques for dynamically assigning jobs to processors in a cluster based on broadcast information | Lakshminarayana B. Arimilli, Claude Basso, Jean Calvignac | 2012-02-21 |
| 8117401 | Interconnect operation indicating acceptability of partial data delivery | Lakshminarayana B. Arimilli, Jerry Don Lewis, Warren E. Maule | 2012-02-14 |
| 8108545 | Packet coalescing in virtual channels of a data processing system in a multi-tiered full-graph interconnect architecture | Lakshminarayana B. Arimilli, Ramakrishnan Rajamony | 2012-01-31 |
| 8108876 | Modifying an operation of one or more processors executing message passing interface tasks | Lakshminarayana B. Arimilli, Ramakrishnan Rajamony, William E. Speight | 2012-01-31 |
| 8108619 | Cache management for partial cache line operations | Lakshminarayana B. Arimilli, Jerry Don Lewis, Warren E. Maule | 2012-01-31 |
| 8095758 | Fully asynchronous memory mover | Robert S. Blackmore, Chulho Kim, Balaram Sinharoy, Hanhong Xue | 2012-01-10 |
| 8095733 | Virtual barrier synchronization cache castout election | Guy L. Guthrie, Michael S. Siegel, William J. Starke, Derek E. Williams | 2012-01-10 |
| 8082315 | Programming idiom accelerator for remote update | Satya P. Sharma, Randal C. Swanberg | 2011-12-20 |
| 8077602 | Performing dynamic request routing based on broadcast queue depths | Lakshminarayana B. Arimilli, Bernard C. Drerup, Jody B. Joyner, Jerry Don Lewis | 2011-12-13 |
| 8051228 | Physical interface macros (PHYS) supporting heterogeneous electrical properties | Daniel M. Dreps, Edward J. Seminaro | 2011-11-01 |
| 8028017 | Virtual controllers with a large data center | Piyush Chaudhary | 2011-09-27 |
| 8024527 | Partial cache line accesses based on memory access patterns | Lakshminarayana B. Arimilli, Jerry Don Lewis, Warren E. Maule | 2011-09-20 |
| 8018095 | Power conversion, control, and distribution system | Edward J. Seminaro, Kevin R. Covi, Gerald J. Fahr, Daniel Barus | 2011-09-13 |
| 8015379 | Wake-and-go mechanism with exclusive system bus response | Satya P. Sharma, Randal C. Swanberg | 2011-09-06 |