Issued Patents All Time
Showing 51–75 of 508 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8327101 | Cache management during asynchronous memory move operations | Robert S. Blackmore, Chulho Kim, Balaram Sinharoy, Hanhong Xue | 2012-12-04 |
| 8316218 | Look-ahead wake-and-go engine with speculative execution | Satya P. Sharma, Randal C. Swanberg | 2012-11-20 |
| 8312458 | Central repository for wake-and-go mechanism | Satya P. Sharma, Randal C. Swanberg | 2012-11-13 |
| 8312464 | Hardware based dynamic load balancing of message passing interface tasks by modifying tasks | Lakshminarayana B. Arimilli, Ramakrishnan Rajamony, William E. Speight | 2012-11-13 |
| 8285971 | Block driven computation with an address generation accelerator | Balaram Sinharoy | 2012-10-09 |
| 8281106 | Specifying an addressing relationship in an operand data structure | Balaram Sinharoy | 2012-10-02 |
| 8275963 | Asynchronous memory move across physical nodes with dual-sided communication | Robert S. Blackmore, Chulho Kim, Balaram Sinharoy, Hanhong Xue | 2012-09-25 |
| 8266381 | Varying an amount of data retrieved from memory based upon an instruction hint | Gheorghe C. Cascaval, Balaram Sinharoy, William E. Speight, Lixin Zhang | 2012-09-11 |
| 8266504 | Dynamic monitoring of ability to reassemble streaming data across multiple channels based on history | Piyush Chaudhary | 2012-09-11 |
| 8255635 | Claiming coherency ownership of a partial cache line of data | Lakshminarayana B. Arimilli, Jerry Don Lewis, Warren E. Maule | 2012-08-28 |
| 8250307 | Sourcing differing amounts of prefetch data in response to data prefetch requests | Gheorghe C. Cascaval, Balaram Sinharoy, William E. Speight, Lixin Zhang | 2012-08-21 |
| 8250396 | Hardware wake-and-go mechanism for a data processing system | Satya P. Sharma, Randal C. Swanberg | 2012-08-21 |
| 8245004 | Mechanisms for communicating with an asynchronous memory mover to perform AMM operations | Robert S. Blackmore, Chulho Kim, Balaram Sinharoy, Hanhong Xue | 2012-08-14 |
| 8239524 | Techniques for dynamically assigning jobs to processors in a cluster based on processor workload | Lakshminarayana B. Arimilli, Claude Basso, Jean Calvignac | 2012-08-07 |
| 8234652 | Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasks | Lakshminarayana B. Arimilli, Ramakrishnan Rajamony, William E. Speight | 2012-07-31 |
| 8230201 | Migrating sleeping and waking threads between wake-and-go mechanisms in a multiple processor data processing system | Satya P. Sharma, Randal C. Swanberg | 2012-07-24 |
| 8225120 | Wake-and-go mechanism with data exclusivity | Satya P. Sharma, Randal C. Swanberg | 2012-07-17 |
| 8214603 | Method and apparatus for handling multiple memory requests within a multiprocessor system | Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke | 2012-07-03 |
| 8214592 | Dynamic runtime modification of array layout for offset | Donald W. Plass, William J. Starke | 2012-07-03 |
| 8214424 | User level message broadcast mechanism in distributed computing environment | Lakshminarayana B. Arimilli, Robert S. Blackmore | 2012-07-03 |
| 8209488 | Techniques for prediction-based indirect data prefetching | Balaram Sinharoy, William E. Speight, Lixin Zhang | 2012-06-26 |
| 8185896 | Method for data processing using a multi-tiered full-graph interconnect architecture | Lakshminarayana B. Arimilli, Ramakrishnan Rajamony, Edward J. Seminaro, William E. Speight | 2012-05-22 |
| 8176026 | Consolidating file system backend operations with access of data | Piyush Chaudhary | 2012-05-08 |
| 8171476 | Wake-and-go mechanism with prioritization of threads | Satya P. Sharma, Randal C. Swanberg | 2012-05-01 |
| 8166277 | Data prefetching using indirect addressing | Balaram Sinharoy, William E. Speight, Lixin Zhang | 2012-04-24 |