Issued Patents All Time
Showing 176–200 of 581 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10529716 | Asymmetric threshold voltage VTFET with intrinsic dual channel epitaxy | Choonghyun Lee, Jingyun Zhang, Takashi Ando, Alexander Reznicek | 2020-01-07 |
| 10529573 | Formation of pure silicon oxide interfacial layer on silicon-germanium channel field effect transistor device | Takashi Ando, Hemanth Jagannathan, Choonghyun Lee, Vijay Narayanan | 2020-01-07 |
| 10522419 | Stacked field-effect transistors (FETs) with shared and non-shared gates | Takashi Ando, Choonghyun Lee, Alexander Reznicek, Jingyun Zhang | 2019-12-31 |
| 10522678 | Vertical transistor pass gate device | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2019-12-31 |
| 10504900 | Enhanced field Resistive RAM integrated with nanosheet technology | Takashi Ando, Alexander Reznicek | 2019-12-10 |
| 10490559 | Gate formation scheme for nanosheet transistors having different work function metals and different nanosheet width dimensions | Takashi Ando, Ruqiang Bao, Choonghyun Lee | 2019-11-26 |
| 10483368 | Single crystalline extrinsic bases for bipolar junction structures | Tak H. Ning, Jeng-Bang Yau, Alexander Reznicek | 2019-11-19 |
| 10453792 | High density antifuse co-integrated with vertical FET | Alexander Reznicek, Miaomiao Wang, Takashi Ando | 2019-10-22 |
| 10453959 | Fin replacement in a field-effect transistor | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Dominic J. Schepis | 2019-10-22 |
| 10438956 | High density programmable e-fuse co-integrated with vertical FETs | Karthik Balakrishnan, Michael A. Guillorn, Alexander Reznicek | 2019-10-08 |
| 10424650 | Single column compound semiconductor bipolar junction transistor fabricated on III-V compound semiconductor surface | Karthik Balakrishnan, Tak H. Ning, Alexander Reznicek | 2019-09-24 |
| 10424585 | Decoupling capacitor on strain relaxation buffer layer | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2019-09-24 |
| 10410926 | Fabricating contacts of a CMOS structure | Lukas Czornomaz, Veeresh V. Deshpande, Vladimir Djara | 2019-09-10 |
| 10395996 | Method for forming a semiconductor structure containing high mobility semiconductor channel materials | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2019-08-27 |
| 10396075 | Very narrow aspect ratio trapping trench structure with smooth trench sidewalls | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2019-08-27 |
| 10396214 | Method of fabricating electrostatically enhanced fins and stacked nanowire field effect transistors | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek | 2019-08-27 |
| 10396152 | Fabrication of perfectly symmetric gate-all-around FET on suspended nanowire using interface interaction | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2019-08-27 |
| 10396154 | Lateral bipolar junction transistor with abrupt junction and compound buried oxide | Kevin K. Chan, Tak H. Ning, Alexander Reznicek | 2019-08-27 |
| 10396198 | Vertical transistor pass gate device | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2019-08-27 |
| 10396202 | Method and structure for incorporating strain in nanosheet devices | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2019-08-27 |
| 10388727 | Stacked indium gallium arsenide nanosheets on silicon with bottom trapezoid isolation | Takashi Ando, Mahmoud Khojasteh, Alexander Reznicek | 2019-08-20 |
| 10388648 | Vertical field effect transistor (VFET) programmable complementary metal oxide semiconductor inverter | Karthik Balakrishnan, Tak H. Ning, Alexander Reznicek | 2019-08-20 |
| 10381438 | Vertically stacked NFETS and PFETS with gate-all-around structure | Jingyun Zhang, Takashi Ando, Choonghyun Lee, Alexander Reznicek | 2019-08-13 |
| 10374039 | Enhanced field bipolar resistive RAM integrated with FDSOI technology | Takashi Ando, Alexander Reznicek | 2019-08-06 |
| 10366984 | Diode connected vertical transistor | Karthik Balakrishnan, Alexander Reznicek | 2019-07-30 |