Issued Patents All Time
Showing 51–75 of 135 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8053819 | Three-dimensional cascaded power distribution in a semiconductor device | Kerry Bernstein, Paul W. Coteus, Allan M. Hartstein, Stephen V. Kosonocky, Ruchir Puri +1 more | 2011-11-08 |
| 8024513 | Method and system for implementing dynamic refresh protocols for DRAM based cache | John E. Barth, Jr., Erik L. Hedberg, Hillery C. Hunter, Peter A. Sandon, Vijayalakshmi Srinivasan +1 more | 2011-09-20 |
| 8020073 | Dynamic memory architecture employing passive expiration of data | Robert K. Montoye, William Robert Reohr | 2011-09-13 |
| 7986543 | Method for achieving very high bandwidth between the levels of a cache hierarchy in 3-dimensional structures, and a 3-dimensional structure resulting therefrom | — | 2011-07-26 |
| 7945765 | Method and structure for asynchronous skip-ahead in synchronous pipelines | Allan M. Hartstein, Hans M. Jacobson, William Robert Reohr | 2011-05-17 |
| 7941728 | Method and system for providing an improved store-in cache | Wing K. Luk, Thomas R. Puzak, Vijayalakshmi Srinivasan | 2011-05-10 |
| 7913202 | Wafer level I/O test, repair and/or customization enabled by I/O layer | Kerry Bernstein, Paul W. Coteus, Ibrahim M. Elfadel, Daniel J. Friedman, Ruchir Puri +3 more | 2011-03-22 |
| 7813815 | Digital measuring system and method for integrated circuit chip operating parameters | Herschel A. Ainspan, Rick A. Rand, Arthur R. Zingher | 2010-10-12 |
| 7724759 | Method for the asynchronous arbitration of a high frequency bus in a long latency environment | Ferenc M. Bozso | 2010-05-25 |
| 7711904 | System, method and computer program product for executing a cache replacement algorithm | Daniel N. Lynch, Thomas R. Puzak | 2010-05-04 |
| 7692944 | 3-dimensional integrated circuit architecture, structure and method for fabrication thereof | Kerry Bernstein, Paul W. Coteus | 2010-04-06 |
| 7684224 | Structure comprising 3-dimensional integrated circuit architecture, circuit structure, and instructions for fabrication thereof | Kerry Bernstein, Paul W. Coteus | 2010-03-23 |
| 7659535 | High speed data channel including a CMOS VCSEL driver and a high performance photodetector and CMOS photoreceiver | Ferenc M. Bozso | 2010-02-09 |
| 7657726 | Context look ahead storage structures | Allan M. Hartstein, Brian R. Prasky, Thomas R. Puzak, Moinuddin K. Qureshi, Vijayalakshmi Srinivasan | 2010-02-02 |
| 7642813 | Error correcting logic system | Kerry Bernstein, John A. Fifield, Paul D. Kartschoke, William A. Klaasen, Norman J. Rohrer | 2010-01-05 |
| 7616470 | Method for achieving very high bandwidth between the levels of a cache hierarchy in 3-dimensional structures, and a 3-dimensional structure resulting therefrom | — | 2009-11-10 |
| 7551453 | Optically connectable circuit board with optical component(s) mounted thereon | Ferenc M. Bozso | 2009-06-23 |
| 7526610 | Sectored cache memory | Robert K. Montoye, Vijayalakshmi Srinivasan | 2009-04-28 |
| 7521950 | Wafer level I/O test and repair enabled by I/O layer | Kerry Bernstein, Paul W. Coteus, Ibrahim M. Elfadel, Daniel J. Friedman, Ruchir Puri +3 more | 2009-04-21 |
| 7518225 | Chip system architecture for performance enhancement, power reduction and cost reduction | John U. Knickerbocker, Chirag S. Patel | 2009-04-14 |
| 7493480 | Method and apparatus for prefetching branch history information | Klaus J. Getzlaff, Allan M. Hartstein, Thomas Pflueger, Thomas R. Puzak, Eric M. Schwarz +1 more | 2009-02-17 |
| 7483325 | Retention-time control and error management in a cache system comprising dynamic storage | William Roehr | 2009-01-27 |
| 7472226 | Methods involving memory caches | Robert K. Montoye, Vijayalakshmi Srinivasan | 2008-12-30 |
| 7471115 | Error correcting logic system | Kerry Bernstein, John A. Fifield, Paul D. Kartschoke, William A. Klaasen, Norman J. Rohrer | 2008-12-30 |
| 7408798 | 3-dimensional integrated circuit architecture, structure and method for fabrication thereof | Kerry Bernstein, Paul W. Coteus | 2008-08-05 |