Issued Patents All Time
Showing 101–125 of 135 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6337287 | High speed, high bandwidth, high density nonvolatile memory system | Ferenc M. Bozso | 2002-01-08 |
| 6285050 | Decoupling capacitor structure distributed above an integrated circuit and method for making same | Wei Hwang, Stephen M. Gates | 2001-09-04 |
| 6271542 | Merged logic and memory combining thin film and bulk Si transistors | Wei Hwang, Stephen M. Gates | 2001-08-07 |
| 6262885 | Portable computing device having a display movable thereabout | Robert K. Montoye | 2001-07-17 |
| 6242950 | Bidirectional data transfer path having increased bandwidth | Ferenc M. Bozso, William Robert Reohr | 2001-06-05 |
| 6076140 | Set associative cache memory system with reduced power consumption | Sang Hoo Dhong, William Robert Reohr, Joel A. Silberman | 2000-06-13 |
| 6067245 | High speed, high bandwidth, high density nonvolatile memory system | Ferenc M. Bozso | 2000-05-23 |
| 6040203 | Clock skew minimization and method for integrated circuits | Ferenc M. Bozso | 2000-03-21 |
| 6038260 | Method and apparatus for transposing differential signals onto a set of binary signals to increase the information-carrying capacity of the original set of signals | Rajiv V. Joshi, William Robert Reohr | 2000-03-14 |
| 6021461 | Method for reducing power consumption in a set associative cache memory system | Sang Hoo Dhong, William Robert Reohr, Joel A. Silberman | 2000-02-01 |
| 6018550 | Method and apparatus for transposing differential signals onto a set of binary signals to increase the information-carrying capacity of the original set of signals | Rajiv V. Joshi, William Robert Reohr | 2000-01-25 |
| 6016267 | High speed, high bandwidth, high density, nonvolatile memory system | Ferenc M. Bozso | 2000-01-18 |
| 6014036 | Bidirectional data transfer path having increased bandwidth | Ferenc M. Bozso, William Robert Reohr | 2000-01-11 |
| 5911153 | Memory design which facilitates incremental fetch and store requests off applied base address requests | Sang Hoo Dhong, William Robert Reohr, Joel A. Silberman | 1999-06-08 |
| 5760478 | Clock skew minimization system and method for integrated circuits | Ferenc M. Bozso | 1998-06-02 |
| 5734764 | Method and apparatus for achieving a fully-connected nonblocking optical crossbar switch having wide transfer paths and minimal latency by exploiting the transparency of silicon at selected wavelengths | Ferenc M. Bozso | 1998-03-31 |
| 5692121 | Recovery unit for mirrored processors | Ferenc M. Bozso, Yiu-Hing Chan, Algirdas J. Gruodis, David P. Hillerud, Scott Barnett Swaney | 1997-11-25 |
| 5636364 | Method for enabling concurrent misses in a cache memory | Joshua W. Knight, Thomas R. Puzak | 1997-06-03 |
| 5634119 | Computer processing unit employing a separate millicode branch history table | Joshua W. Knight, Thomas R. Puzak, James R. Robinson, A. James Van Norstrand, Jr. | 1997-05-27 |
| 5619665 | Method and apparatus for the transparent emulation of an existing instruction-set architecture by an arbitrary underlying instruction-set architecture | — | 1997-04-08 |
| 5584002 | Cache remapping using synonym classes | Joshua W. Knight, Keith N. Langston, James H. Pomerene, Thomas R. Puzak | 1996-12-10 |
| 5434985 | Simultaneous prediction of multiple branches for superscalar processing | Joshua W. Knight, James H. Pomerene, Thomas R. Puzak | 1995-07-18 |
| 5353421 | Multi-prediction branch prediction mechanism | Joshua W. Knight, James H. Po merene, Thomas R. Puzak, Rudolph N. Rechtschaffen, James R. Robinson | 1994-10-04 |
| 5333283 | Case block table for predicting the outcome of blocks of conditional branches having a common operand | David Kaeli | 1994-07-26 |
| 5297281 | Multiple sequence processor system | Joshua W. Knight, James H. Pomerene, Rudolph N. Rechtschaffen, Frank J. Sparacio | 1994-03-22 |