Issued Patents All Time
Showing 76–95 of 95 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6836831 | Independent sequencers in a DRAM control structure | Robert Allen Drehmel, Brian T. Vanderpool | 2004-12-28 |
| 6801982 | Read prediction algorithm to provide low latency reads with SDRAM cache | Brian T. Vanderpool, Lawrence D. Whitley | 2004-10-05 |
| 6760856 | Programmable compensated delay for DDR SDRAM interface using programmable delay loop for reference calibration | James Anthony Marcella | 2004-07-06 |
| 6754858 | SDRAM address error detection method and apparatus | Brian T. Vanderpool | 2004-06-22 |
| 6697935 | Method and apparatus for selecting thread switch events in a multithreaded processor | Richard J. Eickemeyer, William T. Flynn, Andrew Henry Wottreng | 2004-02-24 |
| 6671211 | Data strobe gating for source synchronous communications interface | Todd A. Greenfield, James Anthony Marcella | 2003-12-30 |
| 6600347 | Dynamically producing an effective impedance of an output driver with a bounded variation during transitions thereby reducing jitter | Moises Cases, Daniel M. Dreps, David LeRoy Guertin, Nam H. Pham, Robert R. Williams | 2003-07-29 |
| 6567839 | Thread switch control in a multithreaded processor system | Richard J. Eickemeyer, William T. Flynn, Sheldon B. Levenstein, Andrew Henry Wottreng | 2003-05-20 |
| 6442102 | Method and apparatus for implementing high speed DDR SDRAM read interface with reduced ACLV effects | Todd A. Greenfield | 2002-08-27 |
| 6263404 | Accessing data from a multiple entry fully associative cache buffer in a multithread data processing system | Duane A. Averill | 2001-07-17 |
| 6212544 | Altering thread priorities in a multithreaded processor | William T. Flynn, Andrew Henry Wottreng | 2001-04-03 |
| 6151664 | Programmable SRAM and DRAM cache interface with preset access priorities | Gerald G. Fagerness, John D. Irish, David J. Krolak | 2000-11-21 |
| 6119202 | Method and apparatus to interleave level 1 data cache line fill data between system bus and level 2 data cache for improved processor performance | James Ira Brookhouser | 2000-09-12 |
| 6105051 | Apparatus and method to guarantee forward progress in execution of threads in a multithreaded processor | Richard J. Eickemeyer, William T. Flynn, Steven R. Kunkel, Sheldon B. Levenstein, Andrew Henry Wottreng | 2000-08-15 |
| 6088788 | Background completion of instruction and associated fetch request in a multithread processor | Richard J. Eickemeyer, Sheldon B. Levenstein, Andrew Henry Wottreng, Duane A. Averill, James Ira Brookhouser | 2000-07-11 |
| 6076157 | Method and apparatus to force a thread switch in a multithreaded processor | Richard J. Eickemeyer, William T. Flynn, Andrew Henry Wottreng | 2000-06-13 |
| 6044447 | Method and apparatus for communicating translation command information in a multithreaded environment | Duane A. Averill, James A. Steenburgh, Sandra S. Woodward | 2000-03-28 |
| 5790843 | System for modifying microprocessor operations independently of the execution unit upon detection of preselected opcodes | William T. Flynn, Philip R. Hillier, III, Andrew Henry Wottreng | 1998-08-04 |
| 5067105 | System and method for automatically configuring translation of logical addresses to a physical memory address in a computer memory system | Quentin G. Schmierer, Charles P. Geer | 1991-11-19 |
| 4972414 | Method and apparatus for detecting oscillator stuck faults in a level sensitive scan design (LSSD) system | Steven M. Douskey, Jerome M. Meyer | 1990-11-20 |