Issued Patents All Time
Showing 51–75 of 95 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7675949 | Dynamic reconfiguration of solid state memory device to replicate and time multiplex data over multiple data interfaces | Gerald K. Bartley, William Paul Hovis, Paul Rudrud | 2010-03-09 |
| 7672105 | Production of limited lifetime devices achieved through E-fuses | William Paul Hovis, Daniel P. Kolz, Jack A. Mandelman | 2010-03-02 |
| 7650455 | Spider web interconnect topology utilizing multiple port connection | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Philip Raymond Germann, William Paul Hovis +1 more | 2010-01-19 |
| 7620763 | Memory chip having an apportionable data bus | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki +1 more | 2009-11-17 |
| 7613870 | Efficient memory usage in systems including volatile and high-density memories | Gerald K. Bartley, William H. Cochran, William Paul Hovis, Paul Rudrud | 2009-11-03 |
| 7577793 | Patrol snooping for higher level cache eviction candidate identification | Brian T. Vanderpool | 2009-08-18 |
| 7546410 | Self timed memory chip having an apportionable data bus | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki +1 more | 2009-06-09 |
| 7533198 | Memory controller and method for handling DMA operations during a page copy | Gerald K. Bartley, William Paul Hovis, Daniel P. Kolz | 2009-05-12 |
| 7526692 | Diagnostic interface architecture for memory device | William Paul Hovis, James Anthony Marcella, Paul Rudrud | 2009-04-28 |
| 7496711 | Multi-level memory architecture with data prioritization | Gerald K. Bartley, Philip Raymond Germann, William Paul Hovis | 2009-02-24 |
| 7492662 | Structure and method of implementing power savings during addressing of DRAM architectures | Gerald K. Bartley, Darryl J. Becker, Philip Raymond Germann, William Paul Hovis | 2009-02-17 |
| 7490186 | Memory system having an apportionable data bus and daisy chained memory chips | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki +1 more | 2009-02-10 |
| 7468993 | Dynamic reconfiguration of solid state memory device to replicate and time multiplex data over multiple data interfaces | Gerald K. Bartley, William Paul Hovis, Paul Rudrud | 2008-12-23 |
| 7467260 | Method and apparatus to purge remote node cache lines to support hot node replace in a computing system | Duane A. Averill, Philip Hillier | 2008-12-16 |
| 7392418 | Capacity on demand using signaling bus control | Benjamin F. Carter, Stephen Levesque | 2008-06-24 |
| 7392445 | Autonomic bus reconfiguration for fault conditions | Laura Marie Zumbrunnen | 2008-06-24 |
| 7334070 | Multi-channel memory architecture for daisy chained arrangements of nodes with bridging between memory channels | — | 2008-02-19 |
| 7309911 | Method and stacked memory structure for implementing enhanced cooling of memory devices | Gerald K. Bartley, William H. Cochran, William Paul Hovis, Paul Rudrud | 2007-12-18 |
| 7254663 | Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modes | Gerald K. Bartley, Robert Allen Drehmel, James Anthony Marcella | 2007-08-07 |
| 7251185 | Methods and apparatus for using memory | Sudhir Dhawan, Philip Hillier, Joseph A. Kirscht, Randolph S. Kolvick | 2007-07-31 |
| 7089361 | Dynamic allocation of shared cache directory for optimizing performance | — | 2006-08-08 |
| 7013375 | Configurable directory allocation | Philip Hillier, Russell D. Hoover | 2006-03-14 |
| 6963516 | Dynamic optimization of latency and bandwidth on DRAM interfaces | Herman L. Blackmon, Joseph A. Kirscht, James Anthony Marcella, David A. Shedivy | 2005-11-08 |
| 6940760 | Data strobe gating for source synchronous communications interface | Todd A. Greenfield, James Anthony Marcella | 2005-09-06 |
| 6839816 | Shared cache line update mechanism | Steven R. Kunkel | 2005-01-04 |