Issued Patents All Time
Showing 26–50 of 95 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8037270 | Structure for memory chip for high capacity memory subsystem supporting replication of command data | Gerald K. Bartley, Philip Raymond Germann | 2011-10-11 |
| 8037258 | Structure for dual-mode memory chip for high capacity memory subsystem | Gerald K. Bartley, Philip Raymond Germann | 2011-10-11 |
| 8037251 | Memory compression implementation using non-volatile memory in a multi-node server system with directly attached processor memory | — | 2011-10-11 |
| 8019949 | High capacity memory subsystem architecture storing interleaved data for reduced bus speed | Gerald K. Bartley, Philip Raymond Germann | 2011-09-13 |
| 8010215 | Structure for selecting processors for job scheduling using measured power consumption | Jay S. Bryant, Daniel P. Kolz | 2011-08-30 |
| 7996641 | Structure for hub for supporting high capacity memory subsystem | Gerald K. Bartley, Philip Raymond Germann | 2011-08-09 |
| 7984240 | Memory compression implementation in a system with directly attached processor memory | — | 2011-07-19 |
| 7966455 | Memory compression implementation in a multi-node server system with directly attached processor memory | — | 2011-06-21 |
| 7930483 | Associativity implementation in a system with directly attached processor memory | — | 2011-04-19 |
| 7921271 | Hub for supporting high capacity memory subsystem | Gerald K. Bartley, Philip Raymond Germann | 2011-04-05 |
| 7921264 | Dual-mode memory chip for high capacity memory subsystem | Gerald K. Bartley, Philip Raymond Germann | 2011-04-05 |
| 7882479 | Method and apparatus for implementing redundant memory access using multiple controllers on the same bank of memory | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Philip Raymond Germann, William Paul Hovis | 2011-02-01 |
| 7873773 | Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modes | Gerald K. Bartley, Robert Allen Drehmel, James Anthony Marcella | 2011-01-18 |
| 7865757 | Capacity on demand using signaling bus control | Benjamin F. Carter, Stephen Levesque | 2011-01-04 |
| 7844769 | Computer system having an apportionable data bus and daisy chained memory chips | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki +1 more | 2010-11-30 |
| 7822936 | Memory chip for high capacity memory subsystem supporting replication of command data | Gerald K. Bartley, Philip Raymond Germann | 2010-10-26 |
| 7818512 | High capacity memory subsystem architecture employing hierarchical tree configuration of memory modules | Gerald K. Bartley, Philip Raymond Germann | 2010-10-19 |
| 7809913 | Memory chip for high capacity memory subsystem supporting multiple speed bus | Gerald K. Bartley, Philip Raymond Germann | 2010-10-05 |
| 7802158 | Diagnostic interface architecture for memory device | William Paul Hovis, James Anthony Marcella, Paul Rudrud | 2010-09-21 |
| 7791978 | Design structure of implementing power savings during addressing of DRAM architectures | Gerald K. Bartley, Darryl J. Becker, Philip Raymond Germann, William Paul Hovis | 2010-09-07 |
| 7783793 | Handling DMA operations during a page copy | Gerald K. Bartley, William Paul Hovis, Daniel P. Kolz | 2010-08-24 |
| 7725762 | Implementing redundant memory access using multiple controllers on the same bank of memory | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Philip Raymond Germann, William Paul Hovis | 2010-05-25 |
| 7725620 | Handling DMA requests in a virtual memory environment | Gerald K. Bartley, William Paul Hovis, Daniel P. Kolz | 2010-05-25 |
| 7707379 | Dynamic latency map for memory optimization | Gerald K. Bartley, Philip Raymond Germann, William Paul Hovis | 2010-04-27 |
| 7707463 | Implementing directory organization to selectively optimize performance or reliability | Gerald K. Bartley, William Paul Hovis, Daniel P. Kolz | 2010-04-27 |