Issued Patents All Time
Showing 26–37 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7667470 | Power grid structure to optimize performance of a multiple core processor | Louis Bennie Capps, Jr., Glenn G. Daves, Anand Haridass, Ronald E. Newhart, Michael J. Shapiro | 2010-02-23 |
| 7482180 | Method for determining the impact of layer thicknesses on laminate warpage | Julien Sylvestre, Marco Gauvin, Sylvain Pharand | 2009-01-27 |
| 7454833 | High performance chip carrier substrate | Irving Memis | 2008-11-25 |
| 7420378 | Power grid structure to optimize performance of a multiple core processor | Louis Bennie Capps, Jr., Glenn G. Daves, Anand Haridass, Ronald E. Newhart, Michael J. Shapiro | 2008-09-02 |
| 7312523 | Enhanced via structure for organic module performance | Jon A. Casey, Luc Guerin, David L. Questad, David J. Russell | 2007-12-25 |
| 7268570 | Apparatus and method for customized burn-in of cores on a multicore microprocessor integrated circuit chip | Louis Bennie Capps, Jr., Glenn G. Daves, Joanne Ferris, Anand Haridass, Ronald E. Newhart +1 more | 2007-09-11 |
| 7214886 | High performance chip carrier substrate | Irving Memis | 2007-05-08 |
| 7066740 | Area array package with low inductance connecting device | Luc Guerin, Jean-Luc Landreville, Gerald P. Audet | 2006-06-27 |
| 7017128 | Concurrent electrical signal wiring optimization for an electronic package | Timothy W. Budell, Patrick H. Buffet, Alain Caron | 2006-03-21 |
| 6762367 | Electronic package having high density signal wires with low resistance | Timothy W. Budell, Patrick H. Buffet | 2004-07-13 |
| 6703706 | Concurrent electrical signal wiring optimization for an electronic package | Timothy W. Budell, Patrick H. Buffet, Alain Caron | 2004-03-09 |
| 6461443 | Method and apparatus for continuous cleaning of substrate surfaces using ozone | Mario LEBOEUF, Isabelle Tremblay, Herbert P. R. Wossidlo | 2002-10-08 |