Issued Patents All Time
Showing 101–125 of 147 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7373624 | Method and system for performing target enlargement in the presence of constraints | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2008-05-13 |
| 7370292 | Method for incremental design reduction via iterative overapproximation and re-encoding strategies | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2008-05-06 |
| 7370298 | Method for heuristic preservation of critical inputs during sequential reparameterization | Geert Janssen, Hari Mony, Viresh Paruthi | 2008-05-06 |
| 7367002 | Method and system for parametric reduction of sequential designs | Geert Janssen, Hari Mony, Viresh Paruthi | 2008-04-29 |
| 7367001 | Method, system and computer program product for verification of digital designs using case-splitting via constrained internal signals | Christian Jacobi, Viresh Paruthi, Kai Weber | 2008-04-29 |
| 7360181 | Enhanced structural redundancy detection | Hari Mony, Viresh Paruthi, Fadi Z. Zaraket | 2008-04-15 |
| 7356792 | Method and system for enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2008-04-08 |
| 7350179 | Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables | Geert Janssen, Hari Mony, Viresh Paruthi | 2008-03-25 |
| 7350169 | Method and system for enhanced verification through structural target decomposition | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2008-03-25 |
| 7350166 | Method and system for reversing the effects of sequential reparameterization on traces | Geert Janssen, Hari Mony, Viresh Paruthi | 2008-03-25 |
| 7343573 | Method and system for enhanced verification through binary decision diagram-based target decomposition | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2008-03-11 |
| 7340694 | Method and system for reduction of XOR/XNOR subexpressions in structural design representations | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2008-03-04 |
| 7340704 | Method and system for optimized automated case-splitting via constraints in a symbolic simulation framework | Christian Jacobi, Viresh Paruthi, Kai Weber | 2008-03-04 |
| 7322017 | Method for verification using reachability overapproximation | Hari Mony, Viresh Paruthi, Jiazhao Xu | 2008-01-22 |
| 7315996 | Method and system for performing heuristic constraint simplification | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2008-01-01 |
| 7305636 | Method and system for formal unidirectional bus verification using synthesizing constrained drivers | Tilman Gloekler, Joachim Kneisel, Johannes Koesters | 2007-12-04 |
| 7299432 | Method for preserving constraints during sequential reparameterization | Geert Janssen, Hari Mony, Viresh Paruthi | 2007-11-20 |
| 7290229 | Method and system for optimized handling of constraints during symbolic simulation | Christian Jacobi, Viresh Paruthi, Kai Weber | 2007-10-30 |
| 7284210 | Method for reconfiguration of random biases in a synthesized design without recompilation | Ali S. El-Zein, Daniel Heller, Wolfgang Roesner | 2007-10-16 |
| 7266795 | System and method for engine-controlled case splitting within multiple-engine based verification framework | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2007-09-04 |
| 7260799 | Exploiting suspected redundancy for enhanced design verification | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2007-08-21 |
| 7203915 | Method for retiming in the presence of verification constraints | Hari Mony, Viresh Paruthi, Jiazhao Xu | 2007-04-10 |
| 7093218 | Incremental, assertion-based design verification | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2006-08-15 |
| 7010485 | Method and system of audio file searching | Nadeem Malik, Steven L. Roberts | 2006-03-07 |
| 6993734 | Use of time step information in a design verification system | Hari Mony, Viresh Paruthi, Mark A. Williams | 2006-01-31 |