Issued Patents All Time
Showing 76–100 of 147 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7788618 | Scalable dependent state element identification | Geert Janssen, Robert L. Kanzelman, Viresh Paruthi | 2010-08-31 |
| 7788615 | Computer program product for verification using reachability overapproximation | Hari Mony, Viresh Paruthi, Jiazhao Xu | 2010-08-31 |
| 7779378 | Computer program product for extending incremental verification of circuit design to encompass verification restraints | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2010-08-17 |
| 7765514 | Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables | Geert Janssen, Hari Mony, Viresh Paruthi | 2010-07-27 |
| 7752593 | Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables | Geert Janssen, Hari Mony, Viresh Paruthi | 2010-07-06 |
| 7752583 | System for verification of digital designs using case-splitting via constrained internal signals | Christian Jacobi, Viresh Paruthi, Kai Weber | 2010-07-06 |
| 7743353 | Enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2010-06-22 |
| 7739635 | Conjunctive BDD building and variable quantification using case-splitting | Christian Jacobi, Viresh Paruthi, Jiazhao Xu | 2010-06-15 |
| 7734452 | Method and system for performing ternary verification | Hari Mony, Viresh Paruthi, Matyas A. Sustik | 2010-06-08 |
| 7689943 | Parametric reduction of sequential design | Geert Janssen, Hari Mony, Viresh Paruthi | 2010-03-30 |
| 7624363 | Method and apparatus for performing equivalence checking on circuit designs having differing clocking and latching schemes | Tobias Gemmeke, Nicolas Maeding, Kai Weber | 2009-11-24 |
| 7600209 | Generating constraint preserving testcases in the presence of dead-end constraints | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2009-10-06 |
| 7552407 | Method and system for performing target enlargement in the presence of constraints | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2009-06-23 |
| 7509605 | Extending incremental verification of circuit design to encompass verification restraints | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2009-03-24 |
| 7478344 | Method and system for enhanced verification by closely coupling a structural satisfiability solver and rewriting algorithms | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2009-01-13 |
| 7475370 | System for verification using reachability overapproximation | Hari Mony, Viresh Paruthi, Jiazhao Xu | 2009-01-06 |
| 7458048 | Computer program product for verification of digital designs using case-splitting via constrained internal signals | Christian Jacobi, Viresh Paruthi, Kai Weber | 2008-11-25 |
| 7454680 | Method, system and computer program product for improving efficiency in generating high-level coverage data for a circuit-testing scheme | Steven Farago, Claude Karl Detjens, Anita Devadason | 2008-11-18 |
| 7448005 | Method and system for performing utilization of traces for incremental refinement in coupling a structural overapproximation algorithm and a satisfiability solver | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2008-11-04 |
| 7437690 | Method for predicate-based compositional minimization in a verification environment | Hari Mony, Viresh Paruthi, Fadi A. Zaraket | 2008-10-14 |
| 7421669 | Using constraints in design verification | Hari Mony, Viresh Paruthi, Jiazhao Xu | 2008-09-02 |
| 7398488 | Trace equivalence identification through structural isomorphism detection with on the fly logic writing | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2008-07-08 |
| 7386450 | Generating multimedia information from text information using customized dictionaries | Nadeem Malik, Steven L. Roberts | 2008-06-10 |
| 7380222 | Method and system for performing minimization of input count during structural netlist overapproximation | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2008-05-27 |
| 7380221 | Method and system for reduction of and/or subexpressions in structural design representations | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2008-05-27 |