Issued Patents All Time
Showing 26–50 of 147 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8566764 | Enhanced analysis of array-based netlists via phase abstraction | Michael L. Case, Hari Mony, Paul Joseph Roessler | 2013-10-22 |
| 8527922 | Method and system for optimal counterexample-guided proof-based abstraction | Michael L. Case, Robert L. Kanzelman, Hari Mony | 2013-09-03 |
| 8484591 | Enhancing redundancy removal with early merging | Michael L. Case, Robert L. Kanzelman, Hari Mony | 2013-07-09 |
| 8478574 | Tracking array data contents across three-valued read and write operations | Michael L. Case, Robert L. Kanzelman, Hari Mony | 2013-07-02 |
| 8473882 | Method and system for scalable reduction in registers with SAT-based resubstitution | Michael L. Case, Hari Mony, Viresh Paruthi | 2013-06-25 |
| 8418119 | Logical circuit netlist reduction and model simplification using simulation results containing symbolic values | Michael L. Case, Robert L. Kanzelman, Hari Mony | 2013-04-09 |
| 8418093 | Method and system for design simplification through implication-based analysis | Michael L. Case, Geert Janssen, Robert L. Kanzelman | 2013-04-09 |
| 8418106 | Techniques for employing retiming and transient simplification on netlists that include memory arrays | Michael L. Case, Robert L. Kanzelman, Hari Mony | 2013-04-09 |
| 8413091 | Enhancing redundancy removal with early merging | Michael L. Case, Robert L. Kanzelman, Hari Mony | 2013-04-02 |
| 8407641 | Logic design verification techniques for liveness checking with retiming | Gabor Bobok, Paul Joseph Roessler, Mark A. Williams | 2013-03-26 |
| 8352894 | Verification techniques for liveness checking of logic designs | Paul Joseph Roessler, Ohad Shacham, Jiazhao Xu | 2013-01-08 |
| 8336016 | Eliminating, coalescing, or bypassing ports in memory array representations | Michael L. Case, Robert L. Kanzelman, Hari Mony | 2012-12-18 |
| 8327302 | Techniques for analysis of logic designs with transient logic | Michael L. Case, Robert L. Kanzelman, Hari Mony | 2012-12-04 |
| 8307313 | Minimizing memory array representations for enhanced synthesis and verification | Michael L. Case, Robert L. Kanzelman, Hari Mony | 2012-11-06 |
| 8291359 | Array concatenation in an integrated circuit design | Michael L. Case, Robert L. Kanzelman, Hari Mony | 2012-10-16 |
| 8255848 | Logic design verification techniques for liveness checking with retiming | Gabor Bobok, Paul Joseph Roessler, Mark A. Williams | 2012-08-28 |
| 8245166 | Optimal correlated array abstraction | Michael L. Case, Robert L. Kanzelman, Hari Mony | 2012-08-14 |
| 8201118 | Method and system for dynamic automated hint generation for enhanced reachability analysis | Paul Joseph Roessler, Mark A. Williams, Jiazhao Xu | 2012-06-12 |
| 8201117 | Method for scalable derivation of an implication-based reachable state set overapproximation | Michael L. Case, Geert Janssen, Hari Mony | 2012-06-12 |
| 8201115 | Scalable reduction in registers with SAT-based resubstitution | Michael L. Case, Hari Mony, Viresh Paruthi | 2012-06-12 |
| 8185852 | Performing minimization of input count during structural netlist overapproximation | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2012-05-22 |
| 8181134 | Techniques for performing conditional sequential equivalence checking of an integrated circuit logic design | Michael L. Case, Hari Mony, Jun Sawada | 2012-05-15 |
| 8181131 | Enhanced analysis of array-based netlists via reparameterization | Michael L. Case, Robert L. Kanzelman, Hari Mony | 2012-05-15 |
| 8171437 | Automated convergence of ternary simulation by saturation of deep gates | Michael L. Case, Geert Janssen, Hari Mony | 2012-05-01 |
| 8146034 | Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking within Designs Including Memory Arrays. | Michael L. Case, Robert L. Kanzelman, Hari Mony | 2012-03-27 |