Issued Patents All Time
Showing 51–75 of 147 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8141048 | Sequential encoding for relational analysis (SERA) of a software model | Ali S. El-Zein, Viresh Paruthi, Fadi A. Zaraket | 2012-03-20 |
| 8122403 | Trace containment detection of combinational designs via constraint-based uncorrelated equivalence checking | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2012-02-21 |
| 8086429 | Predicate-based compositional minimization in a verification environment | Hari Mony, Viresh Paruthi, Fadi A. Zaraket | 2011-12-27 |
| 8042075 | Method, system and application for sequential cofactor-based analysis of netlists | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2011-10-18 |
| 8037085 | Predicate selection in bit-level compositional transformations | Hari Mony, Viresh Paruthi, Fadi Z. Zaraket | 2011-10-11 |
| 8015528 | Enhanced verification by closely coupling a structural satisfiability solver and rewriting algorithms | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2011-09-06 |
| 8015523 | Method and system for sequential netlist reduction through trace-containment | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2011-09-06 |
| 7996803 | Automated use of uninterpreted functions in sequential equivalence | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2011-08-09 |
| 7934180 | Incremental speculative merging | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2011-04-26 |
| 7930672 | Incremental design reduction via iterative overapproximation and re-encoding strategies | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2011-04-19 |
| 7921394 | Enhanced verification through binary decision diagram-based target decomposition | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2011-04-05 |
| 7917884 | Enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2011-03-29 |
| 7917874 | Reversing the effects of sequential reparameterization on traces | Geert Janssen, Hari Mony, Viresh Paruthi | 2011-03-29 |
| 7913218 | Reduction of XOR/XNOR subexpressions in structural design representations | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2011-03-22 |
| 7913208 | Optimal simplification of constraint-based testbenches | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2011-03-22 |
| 7913205 | Method and system for reversing the effects of sequential reparameterization on traces | Geert Janssen, Hari Mony, Viresh Paruthi | 2011-03-22 |
| 7908575 | Enhanced verification through binary decision diagram-based target decomposition using state analysis extraction | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2011-03-15 |
| 7882473 | Sequential equivalence checking for asynchronous verification | Yee Ja, Hari Mony, Viresh Paruthi, Barinjato Ramanandray | 2011-02-01 |
| 7882470 | Method for heuristic preservation of critical inputs during sequential reparameterization | Geert Janssen, Hari Mony, Viresh Paruthi | 2011-02-01 |
| 7882459 | Method and system for reduction of AND/OR subexpressions in structural design representations | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2011-02-01 |
| 7856609 | Using constraints in design verification | Hari Mony, Viresh Paruthi, Jiazhao Xu | 2010-12-21 |
| 7831937 | Method and system for reduction of XOR/XNOR subexpressions in structural design representations | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2010-11-09 |
| 7823093 | Method and system for reduction of and/or subexpressions in structural design representations | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2010-10-26 |
| 7793242 | Method and system for performing heuristic constraint simplification | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2010-09-07 |
| 7788616 | Method and system for performing heuristic constraint simplification | Robert L. Kanzelman, Hari Mony, Viresh Paruthi | 2010-08-31 |