Issued Patents All Time
Showing 201–225 of 472 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8412888 | Cache-based speculation of stores following synchronizing operations | William J. Starke, Derek E. Williams | 2013-04-02 |
| 8370595 | Aggregate data processing system having multiple overlapping synthetic computers | Charles F. Marino, William J. Starke, Derek E. Williams | 2013-02-05 |
| 8352712 | Method and system for specualtively sending processor-issued store operations to a store queue with full signal asserted | Robert H. Bell, Jr., Thomas M. Capasso, Hugh Shen, Jeffrey A. Stuecheli | 2013-01-08 |
| 8347036 | Empirically based dynamic control of transmission of victim cache lateral castouts | Robert Alan Cargnoni, Harmony L. Helterhoff, William J. Starke, Jeffrey A. Stuecheli, Phillip G. Williams | 2013-01-01 |
| 8347037 | Victim cache replacement | Thomas L. Jeremiah, William L. McNeil, Piyush C. Patel, William J. Starke, Jeffrey A. Stuecheli | 2013-01-01 |
| 8332588 | Performing a partial cache line storage-modifying operation based upon a hint | Ravi Kumar Arimilli, William J. Starke, Derek E. Williams | 2012-12-11 |
| 8327072 | Victim cache replacement | Thomas L. Jeremiah, William J. Starke, Phillip G. Williams | 2012-12-04 |
| 8327073 | Empirically based dynamic control of acceptance of victim cache lateral castouts | Harmony L. Helterhoff, Thomas L. Jeremiah, Alvan W. Ng, William J. Starke, Jeffrey A. Stuecheli +1 more | 2012-12-04 |
| 8327074 | Synchronizing access to data in shared memory via upper level cache queuing | William J. Starke, Derek E. Williams | 2012-12-04 |
| 8312220 | Mode-based castout destination selection | Harmony L. Helterhoff, William J. Starke, Phillip G. Williams, Jeffrey A. Stuecheli | 2012-11-13 |
| 8296519 | Synchronizing access to data in shared memory via upper level cache queuing | William J. Starke, Derek E. Williams | 2012-10-23 |
| 8291259 | Delete of cache line with correctable error | Harmony L. Helterhoff, Kevin F. Reick, Phillip G. Williams | 2012-10-16 |
| 8285939 | Lateral castout target selection | Harmony L. Helterhoff, Kevin F. Reick, Phillip G. Williams | 2012-10-09 |
| 8281075 | Processor system and methods of triggering a block move using a system bus write command initiated by user code | Lakshminarayana B. Arimilli, Brian Mitchell Bass, David W. Cummings, Bernard C. Drerup, Ronald Nick Kalla +4 more | 2012-10-02 |
| 8254411 | Data processing system, method and interconnect fabric having a flow governor | Leo James Clark, William J. Starke | 2012-08-28 |
| 8230178 | Data processing system and method for efficient coherency communication utilizing coherency domain indicators | James Stephen Fields, Jr., William J. Starke, Jeffrey A. Stuecheli | 2012-07-24 |
| 8230117 | Techniques for write-after-write ordering in a coherency managed processor system that employs a command pipeline | George William Daly, Ross Boyd Leavens, Joseph Gerald McDonald, Michael S. Siegel, William J. Starke +1 more | 2012-07-24 |
| 8225045 | Lateral cache-to-cache cast-in | Alvan W. Ng, Michael S. Siegel, William J. Starke, Derek E. Williams, Phillip G. Williams | 2012-07-17 |
| 8214603 | Method and apparatus for handling multiple memory requests within a multiprocessor system | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, William J. Starke | 2012-07-03 |
| 8214600 | Data processing system and method for efficient coherency communication utilizing coherency domains | James Stephen Fields, Jr., William J. Starke, Jeffrey A. Stuecheli | 2012-07-03 |
| 8209489 | Victim cache prefetching | William J. Starke, Jeffrey A. Stuecheli, Phillip G. Williams | 2012-06-26 |
| 8205136 | Fault tolerant encoding of directory states for stuck bits | Robert H. Bell, Jr., William J. Starke | 2012-06-19 |
| 8205024 | Protecting ownership transfer with non-uniform protection windows | Leo James Clark, James Stephen Fields, Jr., William J. Starke, Derek E. Williams | 2012-06-19 |
| 8195880 | Information handling system with immediate scheduling of load operations in a dual-bank cache with dual dispatch into write/read data flow | Sanjeev Gai, Hugh Shen, William J. Starke | 2012-06-05 |
| 8176254 | Specifying an access hint for prefetching limited use data in a cache hierarchy | Bradly G. Frey, Cathy May, Balaram Sinharoy, Peter K. Szwed | 2012-05-08 |