Issued Patents All Time
Showing 151–175 of 472 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9367348 | Protecting the footprint of memory transactions from victimization | Sanjeev Ghai, Jonathan R. Jackson, Derek E. Williams | 2016-06-14 |
| 9367264 | Transaction check instruction for memory transactions | Bradly G. Frey, Cathy May, Derek E. Williams | 2016-06-14 |
| 9367263 | Transaction check instruction for memory transactions | Bradly G. Frey, Cathy May, Derek E. Williams | 2016-06-14 |
| 9342454 | Nested rewind only and non rewind only transactions in a data processing system supporting transactional storage accesses | Bradly G. Frey, Cathy May, Derek E. Williams | 2016-05-17 |
| 9336142 | Cache configured to log addresses of high-availability data via a non-blocking channel | Sanjeev Ghai, Hien Minh Le, Hugh Shen, Philip G. Williams | 2016-05-10 |
| 9323702 | Increasing coverage of delays through arbitration logic | David W. Cummings, Jonathan R. Jackson | 2016-04-26 |
| 9304936 | Bypassing a store-conditional request around a store queue | Sanjeev Ghai, Hugh Shen, Derek E. Williams | 2016-04-05 |
| 9280465 | Techniques for moving checkpoint-based high-availability log and data directly from a producer cache to a consumer cache | Steven R. Kunkel, Hien Minh Le, Geraint North, William J. Starke | 2016-03-08 |
| 9274952 | Moving checkpoint-based high-availability log and data directly from a producer cache to a consumer cache | Steven R. Kunkel, Hien Minh Le, Geraint North, William J. Starke | 2016-03-01 |
| 9274856 | Improving processor performance for instruction sequences that include barrier instructions | William J. Starke, Derek E. Williams | 2016-03-01 |
| 9251111 | Command rate configuration in data processing system | David J. Krolak, Charles F. Marino, Praveen S. Reddy, Michael S. Siegel | 2016-02-02 |
| 9244725 | Management of transactional memory access requests by a cache memory | Sanjeev Ghai, Jonathan R. Jackson, Derek E. Williams | 2016-01-26 |
| 9244724 | Management of transactional memory access requests by a cache memory | Sanjeev Ghai, Jonathan R. Jackson, Derek E. Williams | 2016-01-26 |
| 9189403 | Selective cache-to-cache lateral castouts | William J. Starke, Jeffrey A. Stuecheli, Derek E. Williams, Thomas R. Puzak | 2015-11-17 |
| 9176876 | Selective cache-to-cache lateral castouts | William J. Starke, Jeffrey A. Stuecheli, Derek E. Williams, Thomas R. Puzak | 2015-11-03 |
| 9110808 | Formation of an exclusive ownership coherence state in a lower level cache upon replacement from an upper level cache of a cache line in a private shared owner state | William J. Starke, Jeffrey A. Stuecheli, Derek E. Williams, Phillip G. Williams | 2015-08-18 |
| 9069701 | Virtual machine failover | Naresh Nayar, Geraint North, William J. Starke | 2015-06-30 |
| 9058260 | Transient condition management utilizing a posted error detection processing protocol | John Steven Dodson, Benjiman L. Goodman, Eric E. Retter, William J. Starke, Jeffrey A. Stuecheli | 2015-06-16 |
| 9058195 | Virtual machines failover | Sanjeev Ghai, Geraint North, William J. Starke, Phillip G. Williams | 2015-06-16 |
| 9058178 | Selective posted data error detection based on request type | Robert Alan Cargnoni, John Steven Dodson, William J. Starke, Jeffrey A. Stuecheli | 2015-06-16 |
| 9047221 | Virtual machines failover | Naresh Nayar, Geraint North, William J. Starke | 2015-06-02 |
| 9032157 | Virtual machine failover | Sanjeev Ghai, Geraint North, William J. Starke, Phillip G. Williams | 2015-05-12 |
| 8990640 | Selective posted data error detection based on request type | Robert Alan Cargnoni, John Steven Dodson, William J. Starke, Jeffrey A. Stuecheli | 2015-03-24 |
| 8959289 | Data cache block deallocate requests | Sanjeev Ghai, William J. Starke, Jeff A. Stuecheli, Derek E. Williams, Phillip G. Williams | 2015-02-17 |
| 8949540 | Lateral castout (LCO) of victim cache line in data-invalid state | Hien Minh Le, Alvan W. Ng, Michael S. Siegel, Derek E. Williams, Phillip G. Williams | 2015-02-03 |