Issued Patents All Time
Showing 151–173 of 173 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9659779 | Method and structure for enabling high aspect ratio sacrificial gates | Kangguo Cheng, Ryan O. Jung, Jeffrey C. Shearer, John R. Sporre, Sean Teehan | 2017-05-23 |
| 9653571 | Freestanding spacer having sub-lithographic lateral dimension and method of forming same | Hsueh-Chung Chen, Su Chen Fan, Dong-Kwon Kim, Sean Lian, Linus Jang | 2017-05-16 |
| 9640640 | FinFET device with channel strain | Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve | 2017-05-02 |
| 9627277 | Method and structure for enabling controlled spacer RIE | Kangguo Cheng, Ryan O. Jung, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre +1 more | 2017-04-18 |
| 9620590 | Nanosheet channel-to-source and drain isolation | Marc A. Bergendahl, Kangguo Cheng, Eric R. Miller, John R. Sporre, Sean Teehan | 2017-04-11 |
| 9608065 | Air gap spacer for metal gates | Marc A. Bergendahl, Kangguo Cheng, Eric R. Miller, John R. Sporre, Sean Teehan | 2017-03-28 |
| 9601347 | Forming semiconductor fins with self-aligned patterning | Kangguo Cheng, Peng Xu | 2017-03-21 |
| 9595613 | Forming semiconductor fins with self-aligned patterning | Kangguo Cheng, Peng Xu | 2017-03-14 |
| 9589958 | Pitch scalable active area patterning structure and process for multi-channel finFET technologies | Sivananda K. Kanakasabapathy, Eric R. Miller, Stuart A. Sieg | 2017-03-07 |
| 9583563 | Conformal doping for punch through stopper in fin field effect transistor devices | Huiming Bu, Sivananda K. Kanakasabapathy, Tenko Yamashita | 2017-02-28 |
| 9576979 | Preventing strained fin relaxation by sealing fin ends | Kangguo Cheng, Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve +3 more | 2017-02-21 |
| 9536744 | Enabling large feature alignment marks with sidewall image transfer patterning | Kangguo Cheng, Sivananda K. Kanakasabapathy, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre +1 more | 2017-01-03 |
| 9536750 | Method for fin formation with a self-aligned directed self-assembly process and cut-last scheme | Cheng Chi, Chi-Chun Liu, Ruilong Xie | 2017-01-03 |
| 9515141 | FinFET device with channel strain | Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve | 2016-12-06 |
| 9502411 | Strained finFET device fabrication | Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Stuart A. Sieg | 2016-11-22 |
| 9496371 | Channel protection during fin fabrication | Russell H. Arndt, Hong He, Gauri Karve, Muthumanickam Sankarapandian | 2016-11-15 |
| 9472506 | Registration mark formation during sidewall image transfer process | David J. Conklin, Allen H. Gabor, Sivananda K. Kanakasabapathy, Byeong Y. Kim, Stuart A. Sieg | 2016-10-18 |
| 9450095 | Single spacer for complementary metal oxide semiconductor process flow | Marc A. Bergendahl, Kangguo Cheng, Jessica Dechene, Eric R. Miller, Jeffrey C. Shearer +2 more | 2016-09-20 |
| 9425196 | Multiple threshold voltage FinFETs | Kangguo Cheng, Ramachandra Divakaruni, Juntao Li | 2016-08-23 |
| 9362179 | Method to form dual channel semiconductor material fins | Kangguo Cheng, Ryan O. Jung, Eric R. Miller, John R. Sporre, Sean Teehan | 2016-06-07 |
| 9331148 | FinFET device with channel strain | Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve | 2016-05-03 |
| 9318574 | Method and structure for enabling high aspect ratio sacrificial gates | Kangguo Cheng, Ryan O. Jung, Jeffrey C. Shearer, John R. Sporre, Sean Teehan | 2016-04-19 |
| 9305845 | Self-aligned quadruple patterning process | Matthew E. Colburn, Sivananda K. Kanakasabapathy, Stuart A. Sieg | 2016-04-05 |