Issued Patents All Time
Showing 226–250 of 501 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8053348 | Method of forming a semiconductor device using a sacrificial uniform vertical thickness spacer structure | Brent A. Anderson | 2011-11-08 |
| 8053314 | Asymmetric field effect transistor structure and method | Brent A. Anderson, Andres Bryant, William F. Clark, Jr. | 2011-11-08 |
| 8039929 | Asymmetrically stressed CMOS FinFET | Brent A. Anderson | 2011-10-18 |
| 8039376 | Methods of changing threshold voltages of semiconductor transistors by ion implantation | William F. Clark, Jr. | 2011-10-18 |
| 8039908 | Damascene gate having protected shorting regions | Brent A. Anderson, Jed H. Rankin | 2011-10-18 |
| 8036022 | Structure and method of using asymmetric junction engineered SRAM pass gates, and design structure | Brent A. Anderson | 2011-10-11 |
| 8022478 | Method of forming a multi-fin multi-gate field effect transistor with tailored drive current | Brent A. Anderson | 2011-09-20 |
| 8017934 | Carbon nanotube based integrated semiconductor circuit | Joerg Appenzeller, AJ KleinOsowski, Richard Q. Williams | 2011-09-13 |
| 8003516 | BEOL interconnect structures and related fabrication methods | Brent A. Anderson, Jed H. Rankin | 2011-08-23 |
| 8003463 | Structure, design structure and method of manufacturing dual metal gate Vt roll-up structure | Brent A. Anderson | 2011-08-23 |
| 7994612 | FinFETs single-sided implant formation | Brent A. Anderson, Andres Bryant, Josephine B. Chang, Omer H. Dokumaci | 2011-08-09 |
| 7993989 | Vertical spacer forming and related transistor | Brent A. Anderson | 2011-08-09 |
| 7984394 | Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same | Brent A. Anderson, Jeanne P. Bickford, Markus Buehler, Jason D. Hibbeler, Juergen Koehl | 2011-07-19 |
| 7982269 | Transistors having asymmetric strained source/drain portions | Brent A. Anderson, Andres Bryant | 2011-07-19 |
| 7981772 | Methods of fabricating nanostructures | Brent A. Anderson, Andres Bryant, Jeffrey W. Sleight | 2011-07-19 |
| 7979836 | Split-gate DRAM with MuGFET, design structure, and method of manufacture | Brent A. Anderson | 2011-07-12 |
| 7971158 | Spacer fill structure, method and design structure for reducing device variation | Brent A. Anderson, Andres Bryant, Jed H. Rankin | 2011-06-28 |
| 7964922 | Structure, design structure and method of manufacturing dual metal gate VT roll-up structure | Brent A. Anderson | 2011-06-21 |
| 7964467 | Method, structure and design structure for customizing history effects of soi circuits | Brent A. Anderson | 2011-06-21 |
| 7964465 | Transistors having asymmetric strained source/drain portions | Brent A. Anderson, Andres Bryant | 2011-06-21 |
| 7960836 | Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same | Brent A. Anderson, Jeanne P. Bickford, Markus Buehler, Jason D. Hibbeler, Juergen Koehl | 2011-06-14 |
| 7960791 | Dense pitch bulk FinFET process by selective EPI and etch | Brent A. Anderson | 2011-06-14 |
| 7952088 | Semiconducting device having graphene channel | Brent A. Anderson | 2011-05-31 |
| 7951678 | Metal-gate high-k reference structure | Brent A. Anderson | 2011-05-31 |
| 7943997 | Fully-depleted low-body doping field effect transistor (FET) with reverse short channel effects (SCE) induced by self-aligned edge back-gate(s) | James W. Adkisson, Brent A. Anderson, Andres Bryant, William F. Clark, Jr. | 2011-05-17 |