Issued Patents All Time
Showing 76–91 of 91 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8458634 | Latch clustering with proximity to local clock buffers | Charles J. Alpert, Zhuo Li, Gi-Joon Nam, David A. Papa, Natarajan Viswanathan | 2013-06-04 |
| 8443324 | Routing and timing using layer ranges | Charles J. Alpert, Shiyan Hu, Zhuo Li | 2013-05-14 |
| 8418108 | Accuracy pin-slew mode for gate delay calculation | Charles J. Alpert, Zhuo Li, Gi-Joon Nam, David A. Papa, Natarajan Viswanathan +1 more | 2013-04-09 |
| 8418113 | Consideration of local routing and pin access during VLSI global routing | Charles J. Alpert, Zhuo Li, Yaoguang Wei | 2013-04-09 |
| 8370782 | Buffer-aware routing in integrated circuit design | Chuck ALPERT, Zhuo Li, Michael D. Moffitt, Paul G. Villarrubia | 2013-02-05 |
| 8281263 | Propagating design tolerances to shape tolerances for lithography | Kanak B. Agarwal, Shayak Banerjee, Sani R. Nassif | 2012-10-02 |
| 8271920 | Converged large block and structured synthesis for high performance microprocessor designs | Minsik Cho, Victor N. Kravets, Smita Krishnaswamy, Dorothy Kucar, Jagannathan Narasimhan +6 more | 2012-09-18 |
| 8108818 | Method and system for point-to-point fast delay estimation for VLSI circuits | Charles J. Alpert, Michael D. Moffitt, Zhuo Li | 2012-01-31 |
| 8104014 | Regular local clock buffer placement and latch clustering by iterative optimization | Ruchir Puri, Haifeng Qian, James D. Warnock | 2012-01-24 |
| 8037438 | Techniques for parallel buffer insertion | Zhuo Li, Charles J. Alpert, Damir A. Jamsek, Ying Zhou | 2011-10-11 |
| 8015532 | Optimal timing-driven cloning under linear delay model | Charles J. Alpert, Zhuo Li, David A. Papa | 2011-09-06 |
| 8010926 | Clock power minimization with regular physical placement of clock repeater components | Charles J. Alpert, Ruchir Puri, Shyam Ramji, Ashish Singh | 2011-08-30 |
| 7890905 | Slew constrained minimum cost buffering | Charles J. Alpert, Arvind K. Karandikar, Tuhin Mahmud, Stephen T. Quay | 2011-02-15 |
| 7761832 | Method for incremental, timing-driven, physical-synthesis optimization under a linear delay model | Charles J. Alpert, Zhuo Li, Tao Luo, David A. Papa | 2010-07-20 |
| 7549137 | Latch placement for high performance and low power circuits | Charles J. Alpert, Shyam Ramji, Paul G. Villarrubia | 2009-06-16 |
| 7448007 | Slew constrained minimum cost buffering | Charles J. Alpert, Arvind K. Karandikar, Tuhin Mahmud, Stephen T. Quay | 2008-11-04 |