CV

Chandramouli Visweswariah

IBM: 98 patents #587 of 70,183Top 1%
Globalfoundries: 3 patents #1,029 of 4,424Top 25%
UI Utopus Insights: 2 patents #53 of 83Top 65%
GU Globalfoundries U.S.: 1 patents #22 of 211Top 15%
📍 Croton-on-Hudson, NY: #2 of 168 inventorsTop 2%
🗺 New York: #511 of 115,490 inventorsTop 1%
Overall (All Time): #13,447 of 4,157,543Top 1%
104
Patents All Time

Issued Patents All Time

Showing 76–100 of 104 patents

Patent #TitleCo-InventorsDate
7856607 System and method for generating at-speed structural tests to improve process and environmental parameter space coverage Gary D. Grise, Peter A. Habitz, Vikram Iyengar, David E. Lackey, Vladimir Zolotov 2010-12-21
7849429 Methods for conserving memory in statistical static timing analysis Jeffrey G. Hemmett, Natesan Venkateswaran, Vladimir Zolotov 2010-12-07
7844932 Method to identify timing violations outside of manufacturing specification limits Nathan C. Buck, John P. Dubuque, Eric A. Foreman, Peter A. Habitz 2010-11-30
7814448 Representing and propagating a variational voltage waveform in statistical static timing analysis of digital circuits Soroush Abbaspour, David J. Hathaway, Jinjun Xiong, Vladimir Zolotov 2010-10-12
7797657 Parameter ordering for multi-corner static timing analysis Nathan C. Buck, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, Kerim Kalafala +2 more 2010-09-14
7743355 Method of achieving timing closure in digital integrated circuits by optimizing individual macros Jun Zhou, David J. Hathaway, Patrick M. Williams 2010-06-22
7739640 Method and apparatus for static timing analysis in the presence of a coupling event and process variation Soroush Abbaspour, Gregory M. Schaeffer 2010-06-15
7698674 System and method for efficient analysis of point-to-point delay constraints in static timing Kerim Kalafala, Revanta Banerji, David J. Hathaway, Jessica Sheridan 2010-04-13
7681157 Variable threshold system and method for multi-corner static timing analysis Nathan C. Buck, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, Kerim Kalafala +2 more 2010-03-16
7620921 IC chip at-functional-speed testing with process coverage evaluation Eric A. Foreman, Gary D. Grise, Peter A. Habitz, Vikram Iyengar, David E. Lackey +2 more 2009-11-17
7555740 Method and system for evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis Nathan C. Buck, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, Kerim Kalafala +2 more 2009-06-30
7512919 System and method for incremental statistical timing analysis of digital circuits 2009-03-31
7480880 Method, system, and program product for computing a yield gradient from statistical timing Jinjun Xiong, Vladimir Zolotov 2009-01-20
7428716 System and method for statistical timing analysis of digital circuits 2008-09-23
7353359 Affinity-based clustering of vectors for partitioning the columns of a matrix Kerim Kalafala, Vasant Rao 2008-04-01
7293248 System and method for accommodating non-Gaussian and non-linear sources of variation in statistical static timing analysis Hongliang Chang, Sambasivan Narayan, Vladimir Zolotov 2007-11-06
7212946 Method, system, and program product for accommodating spatially-correlated variation in a process parameter Natesan Venkateswaran, Lizheng Zhang, Vladimir Zolotov 2007-05-01
7117455 System and method for derivative-free optimization of electrical circuits Steven G. Walker, Katya Scheinberg, Phillip J. Restle 2006-10-03
7117466 System and method for correlated process pessimism removal for static timing analysis Kerim Kalafala, Peihua Qi, David J. Hathaway, Alexander J. Suess 2006-10-03
7111260 System and method for incremental statistical timing analysis of digital circuits 2006-09-19
7093208 Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devices Patrick M. Williams, Ee K. Cho, David J. Hathaway, Mei-Ting Hsu, Lawrence K. Lange +3 more 2006-08-15
7086023 System and method for probabilistic criticality prediction of digital circuits 2006-08-01
7010763 Method of optimizing and analyzing selected portions of a digital integrated circuit David J. Hathaway, Lawrence K. Lange, Patrick M. Williams 2006-03-07
7003747 Method of achieving timing closure in digital integrated circuits by optimizing individual macros Jun Zhou, David J. Hathaway, Patrick M. Williams 2006-02-21
6922819 System and method of optimal waveform shaping 2005-07-26